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Table 40.
1
Register
Address
Bit 7
PHS_DET
0x24
36
N/A
MU_DUTY
0x25
37
MU_DUTY
AUTO_EN
(1)
MU_CNT1
0x26
38
N/A
MU_CNT2
0x27
39
MUDEL[0]
(0)
MU_CNT3
0x28
40
MUDEL[8]
(0)
MU_CNT4
0x29
41
Search_Tol
(1)
1
The two-digit number is the decimal representation of the address.
The status readback bits for the mu controller, if the controller is locked, are as shown in Table 41.
Table 41.
1
Register
Address
MU_STAT1
0x2A
42
1
The two-digit number is the decimal representation of the address.
To read back the present mu delay and phase values, it is necessary to set the read bit high and then low before the values can be read
back.
•
Read—Register 0x26, Bit 3 (set high to read). For subsequent reads, this bit must be brought low, then high again. It cannot be
left high to continuously read the MUDEL value.
•
Mu delay readback—Register 0x28, Bits[7:0] and Register 0x27, Bit 7 (a total of nine bits in the readback; the maximum mu
delay value is d432 or x1B0). This now represents the value the controller locked to, not the starting value of the search.
•
MUD_PH_Readback, Register 0x27, Bits[4:0]—This represents the phase the controller is locked to.
There is a lower speed limit on the DAC clock. The mu controller was not designed to run at DAC clock speeds of 1 GHz and below.
For applications in these frequency ranges, it is recommended that the mu controller be disabled completely.
5.
If synchronizing multiple parts, enable the synchronization controller and ensure that it locks. If synchronization is not necessary,
skip Step 5 and go to Step 6.
Table 42. Master Mode
1
Register
Address
Bit 7
LVDS_REC_
0x10
16
SYNC_
CNT1
FLG_RST
(0)
LVDS_REC_
0x15
21
SYNC_
CNT6
GAIN[1]
(0)
1
The two-digit number is the decimal representation of the address.
Table 43. Slave Mode
1
Register
Address
Bit 7
LVDS_REC_
0x10
16
SYNC_
CNT1
FLG_RST
(0)
LVDS_REC_
0x15
21
SYNC_
CNT6
GAIN[1](0)
1
The two-digit number is the decimal representation of the address.
Bit 6
Bit 5
N/A
PHS_DET
AUTO_EN (1)
POS/NEG (0)
ADJ[5](0)
Slope (0)
Mode[1] (0)
SrchMode[1]
SrchMode
(1)
[0] (0)
MUDEL[7]
MUDEL[6] (1)
(1)
Retry (1)
ContRst (0)
Bit 7
Bit 6
Bit 5
N/A
N/A
N/A
Bit 6
Bit 5
SYNC_
SYNC_
LOOP_ON
MST/SLV
(1)
(1)
SYNC_
SYNCOUT_
PH[1](0)
GAIN[0](1)
Bit 6
Bit 5
SYNC_
SYNC_
LOOP_ON
MST/SLV
(1)
(0)
SYNC_
SYNCOUT_
PH[1](0)
GAIN[0](1)
Bit 4
Bit 3
CMP_BST
Bias[3]
(1)
(0)
ADJ[4] (0)
ADJ[3]
(0)
Mode[0]
Read (0)
(0)
SetPhs[4]
SetPhs
(0)
[3] (0)
MUDEL[5]
MUDEL
(0)
[4] (1)
Guard[4]
Guard[3]
(0)
(1)
Bit 4
Bit 3
Bit 2
N/A
N/A
N/A
Bit 4
Bit 3
Bit 2
SYNC_
N/A
RCVR_
CNT_ENA
FLG_RST
(1)
(0)
SYNCOUT_
LCKTHR[3]
LCKTHR[2]
PH[0](0)
(0)
(0)
Bit 4
Bit 3
Bit 2
SYNC_
N/A
RCVR_
CNT_ENA
FLG_RST
(1)
(0)
SYNCOUT_
LCKTHR[3]
LCKTHR[2]
PH[0](0)
(0)
(0)
Rev. A | Page 51 of 56
Bit 2
Bit 1
Bit 0
Bias[2]
Bias[1]
Bias[0]
(0)
(0)
(0)
ADJ[2]
ADJ[1]
ADJ[0]
(0)
(0)
(0)
Gain[1]
Gain[0]
Enable (1)
(0)
(1)
SetPhs
SetPhs
SetPhs[0]
[2] (1)
[1] (1)
(0)
MUDEL[
MUDEL
MUDEL[1]
3] (1)]
[2] (0)
(0)
Guard
Guard
Guard[0]
[2] (0)
[1] (1)
(1)
Bit 1
Bit 0
MU_LOST (0)
MU_LKD (1)
Bit 1
Bit 0
RCVR_
RCVR_
LOOP_ON
CNT_
(0)
ENA (0)
LCKTHR[1]
LCKTHR[0]
(1)
(0)
Bit 1
Bit 0
RCVR_
RCVR_
LOOP_
CNT_ENA
ON (1)
(1)
LCKTHR[1]
LCKTHR[0]
(1)
(0)
AD9739
Recommended
Value
0x30
0x80
0x03
0x46
0x6C
0xCB
Recommended
Value
0x01
Recommended
Value
0x70
0x42
Recommended
Value
0x50
0x42
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