Analog Devices AD9739 Manual page 31

Table 21. LVDS Control/Status Register Bit Descriptions
Bit Name Read/Write
Read/write
HNDOFF_CHK_RST
LVDS_Bias[1:0] Read/write
Read
HNDOFF_Fall[3:0]
HNDOFF_Rise[3:0] Read
SUP/HLD_Edge1 Read
DCI_PHS3 Read
DCI_PHS1 Read
DCI_PRE_PH2 Read
DCI_PRE_PH0 Read
DCI_PST_PH2 Read
DCI_PST_PH0 Read
SUP/HLD_SYNC Read
SUP/HLD_Edge0 Read
SYNC_SAMP1 Read
SYNC_SAMP0 Read
LVDS1_HI Read
LVDS1_LO Read
LVDS0_HI Read
LVDS0_LO Read
Description
0: default. Bit is in the inactive state.
1: resets the handoff errors in Register 0x0B.
0x0: 360 μA bias current.
0x1: 460 μA bias current.
0x2: 560 μA bias current
0x3: 660 μA bias current.
0: there are no timing violations in the falling edges between the delay lines.
1: there is a timing violation in the falling edges between the delay lines.
0: there are no timing violations in the rising edges between the delay lines.
1: there is a timing violation in the rising edges between the delay lines.
Sample second phase of clock divider with setup/hold delay line.
0: divider phases aligned correctly.
1: divider phases aligned incorrectly.
0: divider phases aligned incorrectly.
1: divider phases aligned correctly.
0: the DCI signal is aligned with the Phase 2 edge.
1: the DCI signal is slightly before the Phase 2 edge.
0: the DCI signal is aligned with the Phase 0 edge.
1: the DCI signal is slightly before the Phase 0 edge.
0: the DCI signal is aligned with the Phase 2 edge.
1: the DCI signal is slightly after the Phase 2 edge.
0: the DCI signal is aligned with the Phase 0 edge.
1: the DCI signal is slightly after the Phase 0 edge.
Sample SYNC_IN with setup/hold delay line (should be between the first phase
and the second phase).
Sample first phase of clock divider with setup/hold delay line.
SYNC_IN sample of clock divider Phase 1.
SYNC_IN sample of clock divider Phase 0.
One or more LVDS inputs on Port 1 are above the input voltage limits of the IEEE
reduce link specification.
One or more LVDS inputs on Port 1 are below the input voltage limits of the IEEE
reduce link specification.
One or more LVDS inputs on Port 0 are above the input voltage limits of the IEEE
reduce link specification.
One or more LVDS inputs on Port 0 are below the input voltage limits of the IEEE
reduce link specification.
Rev. A | Page 31 of 56
AD9739
Reset Value for
Write Register
0x00
0x0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0