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AD9739
Bit Name
Read/Write
MULCK_IRQ
Read
RCVLST_IRQ
Read
RCVLCK_IRQ
Read
Table 16. Full-Scale Current Registers (Register 0x06, Register 0x07)
Register
1
Name
Address
FSC_1
0x06
06
FSC_2
0x07
07
1
The two-digit number is the decimal representation of the address.
Table 17. Full Scale Output Register Bit Descriptions
Bit Name
Read/Write
Sleep
Read/write
FSC[9:0]
Read/write
Table 18. Decoder Control Register (Register 0x08)
Register
Name
Address
Dec_CNT
0x08
1
The two-digit number is the decimal representation of the address.
Table 19. Decoder Control/Status Register Bit Descriptions
Bit Name
Read/Write
DAC_DEC[1:0]
Read/write
Table 20. LVDS Control/Status Registers (Register 0x0A, Register 0x0B, Register 0x0C, Register 0x0D)
Register
Name
1
Address
LVDS_CNT
0x0A
10
DIG_STAT
0x0B
11
LVDS_STAT1
0x0C
12
LVDS_STAT2
0x0D
13
1
The two-digit number is the decimal representation of the address.
Description
0: the mu controller is unlocked.
1: the mu controller has achieved lock and an interrupt has occurred.
0: the RCV controller has not lost lock.
1: the RCV controller has lost lock and an interrupt has occurred.
0: the RCV controller is unlocked.
1: the RCV controller has achieved lock and an interrupt has occurred.
Bit 7
Bit 6
FSC[7]
FSC[6]
Sleep
N/A
Description
0: enable DAC output.
1: set DAC output current to 0 mA.
0x000: 10 mA full-scale output current.
0x200: 20 mA full-scale output current.
0x3FF: 30 mA full-scale output current.
See the Voltage Reference section for full details.
1
Bit 7
Bit 6
08
N/A
N/A
Description
0x0: normal mode.
0x1: return to zero mode.
0x2: analog mix mode.
0x3: flip mode.
Bit 7
Bit 6
Bit 5
N/A
N/A
N/A
HNDOFF_
HNDOFF_
HNDOFF_
Fall[3]
Fall[2]
Fall[1]
SUP/HLD_
N/A
DCI_PHS3
Edge1
SUP/HLD_
SUP/HLD_
SYNC_
SYNC
Edge0
SAMP1
Bit 5
Bit 4
Bit 3
FSC[5]
FSC[4]
FSC[3]
N/A
N/A
N/A
Bit 5
Bit 4
Bit 3
N/A
N/A
N/A
Bit 4
Bit 3
N/A
HNDOFF_
CHK_RST
HNDOFF_
HNDOFF_
Fall[0]
Rise[3]
DCI_PHS1
DCI_PRE_
PH2
LVDS1_HI
SYNC_
SAMP0
Rev. A | Page 30 of 56
Bit 2
Bit 1
FSC[2]
FSC[1]
N/A
FSC[9]
Bit 2
Bit 1
N/A
DAC_DEC[1]
Bit2
Bit 1
N/A
LVDS_
Bias[1]
HNDOFF_
HNDOFF_
Rise[2]
Rise[1]
DCI_PRE_
DCI_PST_
PH0
PH2
LVDS1_LO
LVDS0_HI
Reset Value for
Write Register
0
0
0
Bit 0
FSC[0]
FSC[8]
Reset Value for
Write Register
0
0x200
Bit 0
DAC_DEC[0]
Reset Value for
Write Register
0x0
Bit 0
LVDS_
Bias[0]
HNDOFF_
Rise[0]
DCI_PST_
PH0
LVDS0_LO
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