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To verify that the sync controller is locked and tracking, the following bits must be read back:
•
Register 0x21, Bit 4 (SYNC_LCK)—If the controller is locked, this bit reads back a value of 1. This is a value of 1 for the master
part only. If the part is set up as a slave, this bit reads back 0.
•
Register 0x21, Bit 7 (SYNC_TRK_ON)—If the controller is tracking, this bit reads back a value of 1. This is a value of 1 for the
master part only. If the part is set up as a slave, this bit reads back 0.
•
Register 0x21, Bit 5 (SYNC_LST_LCK)—If the controller is locked, this bit reads back a value of 0. If the controller comes out of
lock, this bit reads back a value of 1. This bit is valid for the master part only.
•
Register 0x0D, Bit 4 (SYNC_SAMP0)—If the controller is locked and the SYNC_IN signal is positioned correctly, this bit reads
back a value of 0. This state is valid for both the master and slave parts.
•
Register 0x0D, Bit 5 (SYNC_SAMP1)—If the controller is locked and the SYNC_IN signal is positioned correctly, this bit reads
back a value of 1. This state is valid for both the master and slave parts.
6.
Load the desired data pattern.
7.
Enable the LVDS controller and ensure that it locks. If the synchronization controller is being used, keep the values from Step 5 in
the registers and add the values in Table 44.
Table 44.
1
Register
Address
Bit 7
LVDS_REC_
0x10
16
SYNC_
CNT1
FLG_RST
(0)
LVDS_REC_
0x11
17
SMP_DEL
CNT2
[1] (1)
LVDS_REC_
0x12
18
SMP_DEL
CNT3
[9] (0)
LVDS_REC_
0x13
19
DCI_DEL
CNT4
[3] (0)
LVDS_REC_
0x14
20
CLKDIVPH
CNT5
[1]] (0)
LVDS_REC_
0x15
21
SYNC_
CNT6
GAIN[1](0)
LVDS_REC_
0x16
22
N/A
CNT7
LVDS_REC_
0x17
23
SYNCSH_
CNT8
DEL[0] (0)
LVDS_REC_
0x18
24
SYNCSH_
CNT9
DEL[8] (0)
1
The two-digit number is the decimal representation of the address.
To verify that the LVDS controller is locked, tracking, and
sampling on the correct phase, the following bits must be read
back:
•
Register 0x21, Bit 0 (RCVR_LCK)—If the controller is
locked, this bit reads back a value of 1.
•
Register 0x21, Bit 3 (RCVR_TRK_ON)—If the controller is
tracking this bit reads back a value of 1.
•
Register 0x0C, Bit 5 (DCI_PHS3)—If the controller is
locked on the correct phase and the data is sampling
correctly, this bit reads back a value of 0.
•
Register 0x0C, Bit 4 (DCI_PHS1)—If the controller is
locked on the correct phase and the data is sampling
correctly, this bit reads back a value of 1.
Bit 6
Bit 5
Bit 4
SYNC_
SYNC_
SYNC_
LOOP_ON
CNT_ENA
MST/SLV
(0)
(0)
(0)
SMP_DEL
FINE_DEL_
FINE_DEL_
MID[3] (0)
MID[2] (1)
[0] (0)
SMP_DEL
SMP_DEL
SMP_DEL
[6] (1)
[8] (0)
[7] (1)
DCI_DEL
DCI_DEL
DCI_DEL
[0] (0)
[2] (1)
[1] (1)
CLKDIVPH
DCI_DEL[9]
DCI_DEL
(0)
[8] (0)
[0] (0)
SYNC_
SYNCOUT_
SYNCOUT_
PH[1](0)
PH[0](0)
GAIN[0](1)
SYNCO_
SYNCO_
SYNCO_
DEL[5] (0)
DEL[6] (0)
DEL[4] (0)
N/A
N/A
N/A
SYNCSH_
SYNCSH_
SYNCSH_
DEL[7] (0)
DEL[6] (0)
DEL[5] (0)
Rev. A | Page 52 of 56
Bit 3
Bit 2
Bit 1
N/A
RCVR_
RCVR_
FLG_RST
LOOP_
(0)
ON (1)
FINE_DEL
FINE_DEL
RCVR_
_MID[1]
_MID[0]
GAIN [1]
(1)
(1)
(0)
SMP_DEL
SMP_DEL
SMP_DEL
[5] (1)
[3] (0)
[4] (0)
FINE_DEL
FINE_DEL
FINE_DEL
_SKW[3]
_SKW[2]
_SKW[1]
(0)
(0)
(1)
DCI_DEL
DCI_DEL
DCI_DEL
[7] (1)
[6] (0)
[5] (1)
LCKTHR[3]
LCKTHR[2]
LCKTHR[1]
(0)
(0)
(1)
SYNCO_
SYNCO_
SYNCO_
DEL[3] (0)
DEL[2] (0)
DEL[1] (0)
N/A
N/A
N/A
SYNCSH_
SYNCSH_
SYNCSH_
DEL[4] (0)
DEL[3] (0)
DEL[2] (0)
•
Register 0x19, Bits [7:6] and Register 0x1A, Bits[7:0]
(SMP_DEL[9:0])—This corresponds to the present sample
delay value that the controller locked to. Continuous
readback of these bits shows how the sample delay value
changes to maintain proper sampling in the presence of
temperature shifts in the system.
•
Register 0x1B, Bits[7:6] and Register 0x1C, Bits[7:0]
(DCI_DEL[9:0])—This corresponds to the present DCI
delay value that the controller locked to. Continuous
readback of these bits shows how the DCI value changes to
maintain proper sampling in the presence of temperature
shifts in the system.
Recommended
Bit 0
Value
RCVR_
0x03 (no sync)
CNT_ENA
0x73 (sync
(1)
master)
0x53 (sync slave)
RCVR_GAIN
0x9D
[0] (1)
SMP_DEL
0x29
[2] (1)
FINE_DEL_
0x62
SKW[0] (0)
DCI_DEL
0x0A
[4] (0)
LCKTHR[0]
0x42
(0)
SYNCO_
0x00
DEL[0] (0)
N/A
0x00
SYNCSH_
0x00
DEL[1] (0)
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