Analog Devices AD9739 Manual page 34

AD9739
Bit Name Read/Write
RCVR_FE_ON Read
RCVR_LST_LCK Read
RCVR_LCK Read
Table 26. Cross Controller Registers (Register 0x22, Register 0x23)
Register
1
Name Address Bit 7
CROSS_ 0x22 34 N/A
CNT1
CROSS_ 0x23 35 N/A
CNT2
1
The two-digit number is the decimal representation of the address.
Table 27. Cross Controller Register Bit Descriptions
Bit Name Read/Write
CLKP_OFFSET[3:0] Read/write
DIR_P Read/Write
CLKN_OFFSET[3:0] Read/write
DIR_N Read/Write
Table 28. MU Controller Registers (Register 0x24, Register 0x25, Register 0x26, Register 0x27, Register 0x28, Register 0x29,
Register 0x2A)
Register
1
Name Address Bit 7
PHS_DET 0x24 36 N/A
MU_DUTY 0x25 37 MU_DUTYAUTO_EN
MU_CNT1 0x26 38 N/A
MU_CNT2 0x27 39 MUDEL[0]
MU_CNT3 0x28 40 MUDEL[8]
MU_CNT4 0x29 41 Search_Tol
MU_STAT1 0x2A 42 N/A
1 The two-digit number is the decimal representation of the address.
Description
0: indicates that the FINDEDGE state machine is not active.
1: indicates that the FINDEDGE state machine is active.
0: lock has not been lost.
1: lock has been lost at some point.
0: the receiver controller is not locked.
1: the receiver controller is locked.
Bit 6 Bit 5
N/A N/A
N/A N/A
Description
0x0: programmable to vary the common-mode voltage for DACCLKP (for best ac
performance, the optimal setting is 15).
O: common-mode voltage on DACCLK_P decreases with the programmed value of
CLKP_OFFSET[3:0].
1: common-mode voltage on DACCLK_P increases with the programmed value of
CLKP_OFFSET[3:0] (for the best ac, the optimal setting is 0).
0x0: programmable to vary the common-mode voltage for DACCLKN (for best ac
performance, the optimal setting is 15).
O: common-mode voltage on DACCLK_N decreases with the programmed value
of CLKN_OFFSET[3:0].
1: common-mode voltage on DACCLK_N increases with the programmed value of
CLKN_OFFSET[3:0] (for the best ac, the optimal setting is 0).
Bit 6 Bit 5
N/A PHS_DETAUTO_EN
POS/NEG ADJ[5]
Slope Mode[1]
SrchMode[1] SrchMode[0]
MUDEL[7] MUDEL[6]
Retry ContRst
N/A N/A
Rev. A | Page 34 of 56
Bit 4 Bit 3
DIR_P CLKP_
OFFSET[3]
DIR_N CLKN_
OFFSET[3]
Bit 4 Bit 3
CMP_BST Bias[3]
ADJ[4] ADJ[3]
Mode[0] Read
SetPhs[4] SetPhs[3]
MUDEL[5] MUDEL[4]
Guard[4] Guard[3]
N/A N/A
Reset Value for
Write Register
0
0
0
Bit 2 Bit 1
CLKP_ CLKP_
OFFSET[2] OFFSET[1]
CLKN_ CLKN_
OFFSET[2] OFFSET[1]
Reset Value for
Write Register
0x0
0
0x0
0
Bit 2 Bit 1
Bias[2] Bias[1]
ADJ[2] ADJ[1]
Gain[1] Gain[0]
SetPhs[2] SetPhs[1]
MUDEL[3] MUDEL[2]
Guard[2] Guard[1]
N/A MU_LOST
Bit 0
CLKP_
OFFSET[0]
CLKN_
OFFSET[0]
Bit 0
Bias[0]
ADJ[0]
Enable
SetPhs[0]
MUDEL[1]
Guard[0]
MU_LKD