Analog Devices AD9739 Manual page 29

Table 11. Power-Down Register Bit Descriptions
Bit Name Read/Write
LVDS_DCO_PD Read/write
LVDS_RCVR_PD Read/write
CLK_REC_PD Read/write
DAC_BIAS_PD Read/write
Table 12. Controller Clock Disable Register (Register 0x02)
Register
Name Address
CNT_CLK_Dis 0x02 02
1
The two-digit number is the decimal representation of the address.
Table 13. Controller Clock Disable Register Bit Descriptions
Bit Name Read/Write
CLKGEN_PD Read/write
REC_CNT_CLK Read/write
MU_CNT_CLK Read/write
Table 14. IRQ Registers (Register 0x03, Register 0x04)
Register
1
Name Address Bit 7
IRQ_En 0x03 03 N/A
IRQ_Req 0x04 04 N/A
1
The two-digit number is the decimal representation of the address.
Table 15. IRQ Register Bit Descriptions
Bit Name Read/Write
SYNC_LST_EN Write
SYNC_LCK_EN Write
MULST_EN Write
MULCK_EN Write
RCV_LST_EN Write
RCV_LCK_EN Write
SYNC_LST_IRQ Read
SYNC_LCK_IRQ Read
MULST_IRQ Read
Description
0: DCO enabled.
1: DCO disabled.
0: LVDS receiver enabled.
1: LSB receiver powered down.
0: internal clock receiver enabled.
1: internal clock receiver powered down.
0: DAC bias circuitry enabled.
1: DAC bias circuitry powered down.
1
Bit 7 Bit 6 Bit 5
N/A N/A N/A
Description
0: clocks enabled.
1: clocks disabled.
0: clock to LVDS receiver controller disabled.
1: clock to LVDS receiver controller enabled.
0: clock to mu controller disabled.
1: clock to mu controller enabled.
Bit 6 Bit 5
N/A SYNC_LST_EN
N/A SYNC_LST_IRQ
Description
0: reset SYNC_LST_IRQ and disable future SYNC_LST_IRQ.
1: enable SYNC_LST_IRQ request.
0: reset SYNC_IRQ and disable future SYNC_LCK_IRQ.
1: enable SYNC_IRQ request.
0: reset MULST_IRQ and disable future MULST_IRQ.
1: enable MULST_IRQ request.
0: reset MULCK_IRQ and disable future MULCK_IRQ.
1: enable the MULCK_IRQ request.
0: reset the RCVLST_IRQ and disable future RCVLST_IRQ.
1: enable the RCVLST_IRQ request.
0: reset the RCV_IRQ interrupt and disable future MULCK_IRQ.
1: enable RCV_IRQ request.
0: the sync controller has not lost lock.
1: the sync controller has lost lock and an interrupt has occurred.
0: the sync controller is unlocked.
1: the sync controller has achieved lock and an interrupt has occurred.
0: the mu controller has not lost lock.
1: the mu controller has lost lock and an interrupt has occurred.
Bit 4 Bit 3
N/A CLKGEN_PD
Bit 4 Bit 3
SYNC_LCK_EN MULST_EN
SYNC_LCK_IRQ MULST_IRQ
Rev. A | Page 29 of 56
Bit 2 Bit 1
N/A REC_CNT_CLK
Bit 2 Bit 1
MULCK_EN RCV_LST_EN
MULCK_IRQ RCVLST_IRQ
AD9739
Reset Value for
Write Register
0
0
0
0
Bit 0
MU_CNT_CLK
Reset Value for
Write Register
0
0
0
Bit 0
RCV_LCK_EN
RCVLCK_IRQ
Reset Value for
Write Register
0
0
0
0
0
0
0
0
0