Analog Devices AD9739 Manual page 38

AD9739
The SYNC_IN_x and SYNC_OUT_x signals are used to
synchronize multiple parts (see the Synchronization Controller
section for more information). Each data port runs internally at
half the speed of the DACCLK_x, and the two ports are subse-
quently multiplexed together to achieve the full DAC update rate.
Maximizing the opening of the eye in the DCI_x and data
signals improves the reliability of the data port interface. The
two sources of degradation that reduce the eye in the DCI_x
and data signals are the jitter on these signals and the skew
between them. Therefore, it is recommended that the DCI_x be
generated in the same manner as the data signals with the same
output driver and data line routing. DCI_x can be implemented
as a 17th data line with an alternating (010101...) bit sequence.
DCI_x
FF
FF
DCI WINDOW
FF
DBx[13:1]
FF
DCI WINDOW
PRE
DCI WINDOW
POST
FINE
DCI WINDOW
DELAY
SAMPLE
PRE
FINE
DELAY
FINE
POST
DELAY
DELAY
SAMPLE
FINE
DELAY
DELAY
FINE
DELAY
SAMPLE
FF
Figure 84. Top Level Diagram of the Data Receiver and Controller
The data receiver behaves like a shift register with a variable
delay from one register to the next. The data receiver uses the
clocks to the rising edge of the DCI_x to determine the proper
data sampling time. Upon enabling the data receiver controller,
the circuit searches for rising edges in both directions, selecting
the closest rising edge. Upon finding the DCI_x rising edge, the
receiver controller enters tracking mode. In tracking mode, the
pre- and post-delay lines traverse the DCI_x edge to maintain
lock and track variations. For proper circuit operation, the DCI_x
and data inputs must maintain a minimum skew (dependent on
frequency). The data receiver controller should be enabled after
the synchronization controller and mu controller indicate a
locked state.
CONTROLLER
SAMPLE
DCI DELAY
DELAY
DELAY DELAY
DELAY DELAY
FF FF
Rev. A | Page 38 of 56
DELAY
PHASE
0
2
/4
1
3
DELAY
FF FF FF
DAC
CLOCK
DATA TO
CORE