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CCDIN
CLPDM
AUX1IN
AUX2IN
FUNCTIONAL BLOCK DIAGRAM
PBLK
AVDD
AVSS
4dB 6dB
CDS
CLP
2:1
BUF
MUX
CLP
AD9843A
Complete 10-Bit 20 MSPS
PRODUCT DESCRIPTION
The AD9843A is a complete analog signal processor for CCD
applications. It features a 20 MHz single-channel architecture
designed to sample and condition the outputs of interlaced and
progressive scan area CCD arrays. The AD9843A's signal chain
consists of an input clamp, correlated double sampler (CDS),
digitally controlled variable gain amplifier (VGA), black level
clamp, and 10-bit A/D converter. Additional input modes are
provided for processing analog video signals.
The internal registers are programmed through a 3-wire serial
digital interface. Programmable features include gain adjust-
ment, black level adjustment, input configuration, and power-
down modes.
The AD9843A operates from a single 3 V power supply, typi-
cally dissipates 78 mW, and is packaged in a 48-lead LQFP.
2dB~36dB
2:1
VGA
MUX
OFFSET
10
DAC
6
8
INTERNAL
REGISTERS
DIGITAL
INTERFACE
SL
SCK
SDATA
CCD Signal Processor
AD9843A
CLPOB
DRVDD
CLP
DRVSS
10
10-BIT
DOUT
ADC
VRT
BANDGAP
REFERENCE
VRB
INTERNAL
CML
BIAS
DVDD
INTERNAL
DVSS
TIMING
SHP
SHD
DATACLK
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Related Manuals for Analog Devices AD9843A
Summary of Contents for Analog Devices AD9843A
- Page 1 Programmable features include gain adjust- ment, black level adjustment, input configuration, and power- down modes. The AD9843A operates from a single 3 V power supply, typi- cally dissipates 78 mW, and is packaged in a 48-lead LQFP. FUNCTIONAL BLOCK DIAGRAM...
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Page 2: General Specifications
AD9843A–SPECIFICATIONS GENERAL SPECIFICATIONS Parameter TEMPERATURE RANGE Operating Storage POWER SUPPLY VOLTAGE Analog, Digital, Digital Driver POWER CONSUMPTION Normal Operation Power-Down Modes Fast Recovery Mode Standby Total Power-Down MAXIMUM CLOCK RATE A/D CONVERTER Resolution Differential Nonlinearity (DNL) No Missing Codes Full-Scale Input Voltage... - Page 3 Steps Guaranteed Steps 63.75 –0.5 +0.5 LSB rms AD9843A = 20 MHz, unless otherwise noted.) Notes See TPC 1 for Power Curves See Input Waveform in Note 1 With 4 dB CDS Gain With –2 dB CDS Gain With 10 dB CDS Gain...
- Page 4 AD9843A–SPECIFICATIONS AUX1-MODE SPECIFICATIONS Parameter POWER CONSUMPTION MAXIMUM CLOCK RATE INPUT BUFFER Gain Max Input Range Max Output Range Gain Control Resolution Gain (Selected Using VGA Gain Register) Min Gain Max Gain Specifications subject to change without notice. AUX2-MODE SPECIFICATIONS Parameter...
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Page 5: Timing Specifications
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9843A features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. - Page 6 AD9843A NC = NO CONNECT Pin Number Name 1, 2 DRVSS 3–12 D0–D9 DRVDD DRVSS 15, 18, 24, 41 DVSS DATACLK DVDD1 PBLK CLPOB CLPDM 25, 26, 35 AVSS AVDD1 BYP1 BYP2 CCDIN BYP4 AVDD2 AUX2IN AUX1IN DVDD2 THREE-STATE STBY SDATA TYPE: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power.
- Page 7 PEAK NONLINEARITY Peak nonlinearity, a full signal chain specification, refers to the peak deviation of the output of the AD9843A from a true straight line. The point used as “zero scale” occurs 1/2 LSB before the first code transition. “Positive full scale” is defined as a Level 1, 1/2 LSB beyond the last code transition.
- Page 8 –Typical Performance Characteristics AD9843A = 3.3V = 3.0V = 2.7V SAMPLE RATE – MHz 0.25 –0.25 –0.5 1000 1000 VGA GAIN CODE – LSB...
- Page 9 3. DIGITAL OUTPUT DATA WILL BE ALL ZEROS DURING PBLK. OUTPUT DATA LATENCY IS 9 DATACLK CYCLES. VIDEO SIGNAL DATACLK OUTPUT N–10 DATA N–9 N–8 HORIZONTAL BLANKING OPTICAL BLACK PIXELS OB PIXEL DATA N–9 N–8 AD9843A N+10 N–1 DUMMY PIXELS EFFECTIVE PIXELS DUMMY BLACK EFFECTIVE DATA N–1...
- Page 10 AD9843A SERIAL INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION Register Address Name A0 A1 A2 Operation Channel Select CCD/AUX VGA Gain Clamp Level Control CDS Gain Internal use only, must be set to zero. Should be set to one. SDATA NOTES: 1.
- Page 11 • • • DATACLK CLP/PBLK 0 Rising Edge Trigger 0 Active Low 1 Falling Edge Trigger 1 Active High AD9843A Power-Down Modes Channel Selection D3 D2 D1 D0 0 Normal Power 1 Fast Recovery 0 Standby 1 Total Power-Down 1 Gain (dB) •...
- Page 12 CCD-Mode Specifications use this default gain setting. However, the CDS gain may be varied to optimize the AD9843A operation in a particular application. Increased CDS gain can be useful with low output level CCDs, while decreased CDS gain allows the AD9843A to accept CCD signal swings greater than 1 V p-p.
- Page 13 Combined with the typical 4 dB gain from the CDS stage, the total gain range for the AD9843A is 6 dB to 40 dB. A gain of 6 dB will match a 1 V input signal with the ADC full-scale range of 2 V.
- Page 14 AD9843A 0.8V 0.1 F INPUT SIGNAL 0.4V AUX2IN VIDEO SIGNAL 0.1 F V-DRIVE 0.4V 0dB TO 36dB AUX1IN 0.4V VGA GAIN REGISTER VGA GAIN REGISTER BUFFER 0dB TO 18dB VIDEO CLAMP CIRCUIT Table VIII. VGA Gain Register Used for AUX2-Mode •...
- Page 15 APPLICATIONS INFORMATION The AD9843A is a complete Analog Front End (AFE) product for digital still camera and camcorder applications. As shown in Figure 16, the CCD image (pixel) data is buffered and sent to the AD9843A analog input through a series input capacitor.
- Page 16 AD9843A OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 48-Lead LQFP (ST-48) 0.063 (1.60) 0.354 (9.00) BSC SQ 0.030 (0.75) 0.018 (0.45) TOP VIEW (PINS DOWN) COPLANARITY 0.003 (0.08) 0.019 (0.5) 0.011 (0.27) 0.008 (0.2) 0.006 (0.17) 0.004 (0.09) 0.006 (0.15) SEATING 0.002 (0.05)