Analog Devices AD9739 Manual page 32

AD9739
Table 22. LVDS Receiver Control Registers (Register 0x10, Register 0x11, Register 0x12, Register 0x13, Register 0x14,
Register 0x15, Register 0x16, Register 0x17, Register 0x18)
Register
1
Name Address Bit 7
LVDS_ 0x10 16 SYNC_
FLG_RST
REC_CNT1
LVDS_ 0x11 17 SMP_DEL[1]
REC_CNT2
LVDS_ 0x12 18 SMP_DEL[9]
REC_CNT3
LVDS_ 0x13 19 DCI_DEL[3]
REC_CNT4
LVDS_ 0x14 20 CLKDIVPH[1]
REC_CNT5
LVDS_ 0x15 21 SYNC_GAIN
[1]
REC_CNT6
LVDS_ 0x16 22 N/A
REC_CNT7
LVDS_ 0x17 23 SYNCSH_
REC_CNT8 DEL[0]
LVDS_ 0x18 24 SYNCSH_
REC_CNT9 DEL[8]
1 The two-digit number is the decimal representation of the address.
Table 23. LVDS Receiver Control Register Bit Descriptions
Bit Name Read/Write
SYNC_FLG_RST Write
SYNC_LOOP_ON Read/write
SYNC_MST/SLV Read/write
SYNC_CNT_ENA Read/write
RCVR_FLG_RST Write
RCVR_LOOP_ON Read/write
RCVR_CNT_ENA Read/write
RCVR_GAIN[1:0] Read/write
SYNC_GAIN[1:0] Read/write
SMP_DEL[9:0] Read/write
FINE_DEL_MID[3:0] Read/write
DCI_DEL[9:0] Read/write
FINE_DEL_SKW[3:0] Read/write
LCKTHR[3:0] Read/write
CLKDIVPH[1:0] Read/write
SYNCO_DEL[6:0] Read/write
SYNCSH_DEL[8:0] Read/write
Bit 6 Bit 5
SYNC_ SYNC_
LOOP_ON
MST/SLV
SMP_DEL [0] FINE_DEL_
MID[3]
SMP_DEL[8] SMP_DEL[7]
DCI_DEL[2] DCI_DEL[1]
CLKDIVPH[0] DCI_DEL[9]
SYNC_GAIN SYNCOUT_
[0] PH[1]
SYNCO_ SYNCO_
DEL[6] DEL[5]
N/A N/A
SYNCSH_ SYNCSH_
DEL[7] DEL[6]
Description
Write high then low to reset flags set by the sync controller.
0: sync controller will not loop or generate an IRQ when an error has occurred.
1: sync controller will generate an IRQ and restart and return to track mode as previous.
0: sync controller is in slave mode.
1: sync controller is in master mode.
0: sync controller is not enabled.
1: sync controller is enabled.
Write high then low to reset flags set by the receiver controller.
0: receiver controller will not loop or generate an IRQ when an error has occurred.
1: receiver controller will generate an IRQ and restart and return to track mode as previous.
0: receiver controller is not enabled.
1: receiver controller is enabled.
Sets the receiver sample tracking gain (optimal value is 1).
Sets the sync tracking gain (optimal value is 1).
Sets the sample delay value (only valid when the data receiver controller is disabled; maximum
sample delay value is 332 or 0x14C). When the data receiver controller is enabled, this represents the
starting point for the search (optimal value is 166 or 0xA6).
Sets the fine delay line mid value (optimal value is 7).
Sets the DCI delay value (only valid when the data receiver controller is disabled; maximum DCI delay
value is 332 or 0x14C). When the data receiver controller is enabled, this represents the starting point
for the search (optimal value is 166 or 0xA6).
Sets the distance between the DCI pre and post sampling.
Sets the difference between the sample and DCI delays to lock (optimal value is 2).
Sets the clock divider phase (only valid when the sync controller is disabled).
Sets the sync output delay value (only valid when the sync controller is disabled).
Sets the sync setup and hold delay value (only valid when the sync controller is disabled).
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Bit 4 Bit 3 Bit 2
SYNC_ N/A RCVR_
CNT_ENA FLG_RST
FINE_DEL_ FINE_DEL_ FINE_DEL_
MID[2] MID[1] MID[0]
SMP_DEL[6] SMP_DEL[5] SMP_DEL[4]
DCI_DEL[0] FINE_DEL_ FINE_DEL_
SKW[3]
SKW[2]
DCI_DEL[8] DCI_DEL[7 DCI_DEL[6]
SYNCOUT_ LCKTHR[3] LCKTHR[2]
PH[0]
SYNCO_ SYNCO_ SYNCO_
DEL[4] DEL[3] DEL[2]
N/A N/A N/A
SYNCSH_ SYNCSH_ SYNCSH_
DEL[5] DEL[4] DEL[3]
Bit 1 Bit 0
RCVR_ RCVR_
LOOP_ON CNT_ENA
RCVR_GAIN[1] RCVR_GAIN[0]
SMP_DEL[3] SMP_DEL[2]
FINE_DEL_ FINE_DEL_
SKW[1] SKW[0]
DCI_DEL[5] DCI_DEL[4]
LCKTHR[1] LCKTHR[0]
SYNCO_ SYNCO_
DEL[1] DEL[0]
N/A N/A
SYNCSH_ SYNCSH_
DEL[2] DEL[1]