Applying Data To The Ad9739 - Analog Devices AD9739 Manual

AD9739
Clock Phase Noise Affects on AC Performance
The quality of the clock source driving the
determines the achievable ACLR performance for the AD9739.
Table 32 summarizes the close-in ACLR for an eight-carrier
DOCSIS signal at 920 MHz with respect to various phase noise
profiles.
Table 32. Eight-Carrier DOCSIS Close-In ACLR
Performance at 920 MHz for Various Phase Noise Profiles
Phase Phase
Noise Noise
Band Profile 1 Profile 2
750 kHz −68.5 −65
to 6 MHz
6 MHz to −68 −66.5
12 MHz
12 MHz −68 −67.5
to 18
MHz
1 All ACLR numbers are specified in decibels relative to the carrier (dBc).
Table 33 shows the phase noise at various offsets for each profile.
Table 33. Phase Noise Summary for Each Profile
Offset Profile 1 Profile 2
1 kHz −111.3 −109.3
10 kHz −117.4 −115.9
100 kHz −123.7 −120.3
1 MHz −141.2 −125.8
10 MHz −150.4 −147.2
100 MHz −150.4 −150.3
1 All phase noise numbers are specified in dBc/Hz.
ORIGINAL
DATA
FILE
DB0
DB1
DEINTERLEAVE
DB2
FILE
DB3
DB4
DB5
ADCLK914
1
Phase Phase
Noise Noise
Profile 3 Profile 4 Spec
−61.1 −56 −59.3
−64 −60 −61.8
−67.3 −67.6 −64
1
Profile 3 Profile 4
−109.25 −107.5
−114.6 −114
−117.3 −114.4
−122 −115.6
−124.6 −117.9
−150.6 −150.6
DB0, DB2, DB4...
DB0[13:0]P
DB0[13:0]N
DB1, DB3, DB5...
DB1[13:0]P
DB1[13:0]N
Figure 87. Graphical Representation of How to Present Data to the AD9739
Rev. A | Page 40 of 56
To still meet the close-in ACLR requirements for the eight-
carrier DOCSIS, the phase noise found in Profile 3 is the
minimum requirement necessary.

APPLYING DATA TO THE AD9739

As explained in the LVDS Data Port Interface section, each data
port runs internally at half the speed of the DACCLK_x, and
the two ports are subsequently multiplexed together to achieve
the full DAC update rate. If the user is creating a data file to
load into the AD9739, this data file must be deinterleaved and
applied to each port, as shown in Table 34.
Table 34. Application of Deinterleaved Files to Ports
Original Data File Apply to DB0[13:0]
DB0 Yes
DB1 No
DB2 Yes
DB3 No
DB4 Yes
DB5 No
A graphical representation of this can be seen in Figure 87. If
the data pattern generator (DPG2) is being used to apply data to
the part, the deinterleaving process can be done automatically
via the software. Thus, the user can apply a single data file using
the DPG2 and allow the software to do the deinterleaving and
apply the correct data to each port.
DB0, DB1, DB2,
14-BIT, 12-BIT,
DB3, DB4...
10-BIT DAC
Apply to DB1[13:0]
No
Yes
No
Yes
No
Yes
IOUTP
CORE IOUTN