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Epson S1C31W73 Technical Manual

Cmos 32-bit single chip microcontroller

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CMOS 32-BIT SINGLE CHIP MICROCONTROLLER

S1C31W73

Technical Manual

Rev. 1.1

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Summary of Contents for Epson S1C31W73

Page 1 CMOS 32-BIT SINGLE CHIP MICROCONTROLLER S1C31W73 Technical Manual Rev. 1.1...
Page 2 2. This evaluation board/kit or development tool is intended for use by an electronic engineer and is not a consumer product. The user should use it properly and in a safe manner. Seiko Epson does not assume any responsibility or liability of any kind of damage and/or fire caused by its use.
Page 3 PREFACE Preface This is a technical manual for designers and programmers who develop a product using the S1C31W73. This document describes the functions of the IC, embedded peripheral circuit operations, and their control methods. Notational conventions and symbols in this manual Register address Peripheral circuit chapters do not provide control register addresses.
Page 4 CLG Oscillation Frequency Trimming Register 2 ..............2-27 3 CPU and Debugger ......................3-1 3.1 Overview ......................... 3-1 3.2 CPU ..........................3-1 3.3 Debugger ........................3-1 3.3.1 List of Debugger Input/Output Pins ..............3-1 Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 5 DMAC Software Request Register ................... 6-11 DMAC Request Mask Set Register ..................6-11 DMAC Request Mask Clear Register ..................6-12 DMAC Enable Set Register ...................... 6-12 DMAC Enable Clear Register ....................6-12 Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 6 7.7.11 Common Registers between Port Groups............. 7-21 8 Universal Port Multiplexer (UPMUX) ................8-1 8.1 Overview ......................... 8-1 8.2 Peripheral Circuit I/O Function Assignment ..............8-1 8.3 Control Registers ......................8-2 Pxy–xz Universal Port Multiplexer Setting Register ..............8-2 Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 7 11.3.3 Clock Supply in DEBUG Mode ..............11-3 11.4 Operations ........................11-3 11.4.1 SVD4 Control ....................11-3 11.4.2 SVD4 Operations ................... 11-4 11.5 SVD4 Interrupt and Reset .................... 11-4 11.5.1 SVD4 Interrupt ....................11-4 11.5.2 SVD Reset ...................... 11-5 Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 8 13.5.3 Data Reception ....................13-6 13.5.4 IrDA Interface ....................13-7 13.5.5 Carrier Modulation ..................13-8 13.6 Receive Errors ......................13-9 13.6.1 Framing Error ....................13-9 13.6.2 Parity Error ..................... 13-9 13.6.3 Overrun Error ....................13-9 Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 9 15.2.2 External Connections ..................15-2 15.2.3 Pin Functions in Master Mode and Slave Mode ..........15-6 15.2.4 Input Pin Pull-Up/Pull-Down Function ............15-6 15.3 Clock Settings ......................15-6 15.3.1 QSPI Operating Clock ................... 15-6 Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 10 16.4.8 Automatic Bus Clearing Operation ............... 16-15 16.4.9 Error Detection ....................16-16 16.5 Interrupts ........................16-17 16.6 DMA Transfer Requests ....................16-18 16.7 Control Registers ......................16-18 I2C Ch.n Clock Control Register ..................... 16-18 Seiko Epson Corporation viii S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 11 18.4.1 Initialization ....................18-3 18.4.2 Buzzer Output in Normal Buzzer Mode ............18-3 18.4.3 Buzzer Output in One-shot Buzzer Mode............18-6 18.4.4 Output in Melody Mode ................. 18-7 18.5 Interrupts ........................18-9 Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 12 20.4.3 Conversion Mode and Analog Input Pin Settings .......... 20-4 20.4.4 A/D Conversion Operations and Control Procedures ........20-4 20.5 Interrupts ........................20-6 20.6 DMA Transfer Requests ....................20-6 20.7 Control Registers ......................20-7 ADC12A Ch.n Control Register ....................20-7 Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 13 22.7 Interrupt ........................22-27 22.8 Control Registers ......................22-27 LCD32C Clock Control Register ..................... 22-27 LCD32C Control Register ......................22-28 LCD32C Timing Control Register 1 ..................22-28 LCD32C Timing Control Register 2 ..................22-29 Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 14 24.5.9 FIFO Management ..................24-17 24.5.10 Snooze ......................24-19 24.6 Interrupts ........................24-20 24.7 DMA Transfer Requests ....................24-21 24.8 Control Registers ......................24-21 USB Control Register ......................24-21 USB Transceiver Control Register ................... 24-23 Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 15 25.15 12-bit A/D Converter (ADC12A) Characteristics ............25-18 25.16 Temperature Sensor/Reference Voltage Generator (TSRVR) Characteristics ... 25-19 25.17 USB 2.0 FS Device Controller (USB) Characteristics ..........25-20 26 Basic External Connection Diagram ...............26-1 Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL xiii (Rev. 1.1)
Page 16 B.1 Operating Status Configuration Examples for Power Saving ........AP-B-1 B.2 Other Power Saving Methods ..................AP-B-2 Appendix C Mounting Precautions ................AP-C-1 Appendix D Measures Against Noise ................ AP-D-1 Revision History Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 17 1 OVERVIEW 1 Overview The S1C31W73 is a 32-bit MCU with an Arm Cortex -M0+ processor included that features low-power operation. It ® ® incorporates a lot of serial interface circuits and is suitable for various kinds of battery-driven controller applications.
Page 18 Flash programming 2.2 to 5.5 V operating voltage when LCD driver is used 1.8 to 5.5 V Operating temperature Operating temperature range -40 to 105°C Flash programming temperature range -40 to 85°C Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 19 P1–5 USIN0–1 (UART3) USOUT0–1 2 Ch. P6–7 Synchronous SDI0–1 RFIN0 serial interface SDO0–1 R/F converter REF0 (SPIA) (RFC) SPICLK0–1 SENA0 2 Ch. 1 Ch. SENB0 #SPISS0–1 RFCLKO0 Figure 1.2.1 S1C31W73 Block Diagram Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 20 N.C. SEG12 SEG12 N.C. N.C. USB18VOUT USB18VOUT N.C. N.C. N.C. N.C. USB_DP USB_DP N.C. N.C. N.C. N.C. N.C. N.C. USB_DM USB_DM N.C. N.C. N.C. N.C. Figure 1.3.1.1 S1C31W73 Pin Configuration Diagram (QFP21-216PIN) Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 21 SEG13 SEG13 SEG12 SEG12 USB18VOUT USB18VOUT USB_DP USB_DP USB_DM USB_DM 4.735 mm Figure 1.3.2.1 S1C31W73 Pad Configuration Diagram Pad opening: X = 68 µm, Y = 68 µm Chip thickness: 400 µm Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 22 1 OVERVIEW Table 1.3.2.1 S1C31W73 Pad Coordinates X µm Y µm X µm Y µm X µm Y µm X µm Y µm -2,063.5 -2,273.0 2,288.0 -2,117.5 1,841.0 2,273.0 -2,288.0 2,002.0 -1,983.5 -2,273.0 2,288.0 -1,837.5 1,758.0 2,273.0 -2,288.0 1,922.0 -1,903.5 -2,273.0 2,288.0 -1,542.5...
Page 23 User-selected I/O (universal port multiplexer) Hi-Z I/O port ✓ RFIN0 R/F converter Ch.0 oscillation input UPMUX User-selected I/O (universal port multiplexer) Hi-Z I/O port ✓ BZOUT Sound generator output UPMUX User-selected I/O (universal port multiplexer) Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 24 User-selected I/O (universal port multiplexer) ADIN04 12-bit A/D converter Ch.0 analog signal input 4 Hi-Z – I/O port UPMUX User-selected I/O (universal port multiplexer) ADIN05 12-bit A/D converter Ch.0 analog signal input 5 Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 25 COM28 LCD common output SEG83 LCD segment output Hi-Z I/O port ✓ COM29 LCD common output SEG82 LCD segment output Hi-Z I/O port ✓ COM30 LCD common output SEG81 LCD segment output Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 26 – USB 1.8 V regulator output USB33VOUT USB33VOUT – – USB 3.3 V regulator output Note: In the peripheral circuit descriptions, the assigned signal name is used as the pin name. Seiko Epson Corporation 1-10 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 27 T16B Ch.n PWM output/capture input 1 TOUTn2/CAPn2 T16B Ch.n PWM output/capture input 2 TOUTn3/CAPn3 T16B Ch.n PWM output/capture input 3 Note: Do not assign a function to two or more pins simultaneously. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 1-11 (Rev. 1.1)
Page 28 For the V operating voltage range and recommended external parts, refer to “Recommended Operating Condi- tions, Power supply voltage V ” in the “Electrical Characteristics” chapter and the “Basic External Connection Diagram” chapter, respectively. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 29 6. Write a value other than 0x0096 to the SYSPROT.PROT[15:0] bits. (Set system protection) Note: After the voltage mode has been switched, correct the RTC, as the RTC operating clock is also stopped for the period set using the CLGOSC1.OSC1WT[1:0] bits. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 30 Supply voltage detector reset circuit SVDRSTREQ Reset request from CPU SYSRST_S0_0 Software reset 0 To peripheral circuit 0 Reset decoder SYSRST_S0_n Software reset n To peripheral circuit n Figure 2.2.1.1 SRC Configuration Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 31 This makes it possible to put the system into reset state if the IC must be stopped under a low voltage condition. For more information, refer to the “Supply Volt- age Detector” chapter. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 32 The #RESET pin has a built-in pull-up resistor and it can be disabled by setting the SRCRESETPCTL.PORT_ PLUP_EN bit to 0. PORT_PLUP_EN PORT_RESET_EN #RESET pin reset request signal #RESET Figure 2.2.5.1 #RESET Pin Input Control Circuit Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 33 POR and BOR Peripheral circuit software reset Reset state is canceled immediately (MODEN and SFTRST bits. The after the reset request is canceled. software reset operations de- pend on the peripheral circuit. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 34 Ceramic3 EXOSCEN EXOSC EXOSC EXOSCCLK clock input circuit FOUTEN Peripheral circuit 1 FOUT FOUT Clock output CLKSRC[x:0] selector circuit CLKDIV[x:0] FOUTDIV[2:0] Peripheral circuit n Clock CLKSRC[x:0] selector CLKDIV[x:0] Figure 2.3.1.1 CLG Configuration Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 35 For more information on the auto- trimming function and the oscillation characteristics, refer to “IOSC oscillation auto-trimming function” in this chapter and “IOSC oscillator circuit characteristics” in the “Electrical Characteristics” chapter, respectively. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 36 OSC2 pin open. For the recommended parts and the oscillation characteristics, refer to the “Basic External Connection Diagram” chapter and “OSC1 oscillator circuit characteristics” in the “Electrical Characteristics” chapter, respectively. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 37 Figure 2.3.4.1 shows the relationship be- tween the oscillation start time and the oscillation stabilization waiting time. Seiko Epson Corporation 2-10 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 38 Oscillator circuit enable (CLGOSC.OSC1EN) Oscillation inverter INV1B[1:0] setting gain INV1N[1:0] setting gain Oscillation waveform Startup boosting Normal operation operation Figure 2.3.4.2 Operation Example when the Oscillation Startup Control Circuit is Used Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 2-11 (Rev. 1.1)
Page 39 3. Write 0x0096 to the SYSPROT.PROT[15:0] bits. (Remove system protection) 4. Configure the following CLGOSC3 register bits. - CLGOSC3.OSC3WT[2:0] bits (Set oscillation stabilization waiting time) - CLGOSC3.OSC3INV[1:0] bits (Set oscillation inverter gain) Seiko Epson Corporation 2-12 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 40 This allows flexible clock control according to the wake-up process. Configure the clock using the CLGSCLK.WUPSRC[1:0] and CLGSCLK.WUPDIV[1:0] bits, and write 1 to the CLGSCLK.WUPMD bit to enable this function. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 2-13 (Rev. 1.1)
Page 41 10 ms is required. When IOSCCLK is being used as the system clock or a peripheral circuit clock, do not use the auto-trimming function. Seiko Epson Corporation 2-14 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 42 This mode can be set while no software processing is required and it reduces power consumption as compared with RUN mode. HALT mode is classified into “IOSC HALT,” “OSC1 HALT,” “OSC3 HALT,” and “EXOSC HALT” by the SYSCLK clock source. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 2-15 (Rev. 1.1)
Page 43 The conditions listed below generate the HALT/SLEEP cancelation signal to cancel HALT or SLEEP mode and put the CPU into RUN mode. • Interrupt request from a peripheral circuit • NMI from the watchdog timer • Reset request Seiko Epson Corporation 2-16 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 44 Bits 3–2 Reserved Bits 1–0 REGMODE[1:0] These bits control the V regulator operating mode. Table 2.6.1 Internal Regulator Operating Mode PWGACTL.REGMODE[1:0] bits Operating mode Economy mode Normal mode Reserved Automatic mode Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 2-17 (Rev. 1.1)
Page 45 0 (R/WP): Disable pull-up Bit 0 PORT_RESET_EN This bit enables the #RESET pin to input the external reset signal. 1 (R/WP): Enable external reset input 0 (R/WP): Disable external reset input Seiko Epson Corporation 2-18 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 46 These bits set the division ratio of the clock source to determine the SYSCLK frequency. Bits 3–2 Reserved Bits 1–0 CLKSRC[1:0] These bits select the SYSCLK clock source. When a currently stopped clock source is selected, it will automatically start oscillating or clock input. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 2-19 (Rev. 1.1)
Page 47 Stop oscillating or clock input Each bit corresponds to the clock source as follows: CLGOSC.EXOSCEN bit: EXOSC clock input CLGOSC.OSC3EN bit: OSC3 oscillator circuit CLGOSC.OSC1EN bit: OSC1 oscillator circuit CLGOSC.IOSCEN bit: IOSC oscillator circuit Seiko Epson Corporation 2-20 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 48 IOSCFQ[2:0] bits voltage mode = mode0 voltage mode = mode1 32 MHz 24 MHz 16 MHz Setting prohibited 12 MHz 8 MHz Setting prohibited 2 MHz 2 MHz 1 MHz 1 MHz Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 2-21 (Rev. 1.1)
Page 49 For more information, refer to “OSC1 oscillator circuit characteristics, Internal gate capacitance C ” in the “Electrical Characteristics” chapter. Bits 7–6 INV1B[1:0] These bits set the oscillation inverter gain that will be applied at boost startup of the OSC1 oscillator circuit. Seiko Epson Corporation 2-22 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 50 Table 2.6.10 OSC3 Oscillation Inverter Gain Setting CLGOSC3.OSC3INV[1:0] bits Inverter gain Max. ↑ ↓ Min. Bit 3 Reserved Bits 2–0 OSC3WT[2:0] These bits set the oscillation stabilization waiting time for the OSC3 oscillator circuit. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 2-23 (Rev. 1.1)
Page 51 CLGINTF.OSC1STAIF bit: OSC1 oscillation stabilization waiting completion interrupt CLGINTF.IOSCSTAIF bit: IOSC oscillation stabilization waiting completion interrupt Note: The CLGINTF.IOSCSTAIF bit is 0 after system reset is canceled, but IOSCCLK has already been stabilized. Seiko Epson Corporation 2-24 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 52 6–4 FOUTDIV[2:0] 3–2 FOUTSRC[1:0] – – FOUTEN Bits 15–7 Reserved Bits 6–4 FOUTDIV[2:0] These bits set the FOUT clock division ratio. Bits 3–2 FOUTSRC[1:0] These bits select the FOUT clock source. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 2-25 (Rev. 1.1)
Page 53 Be aware that the frequency characteristics may not be sat- isfied when these settings are altered. When altering these settings, always make sure that the IOSC oscillator circuit is inactive. Seiko Epson Corporation 2-26 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 54 “Electrical Characteristics” chapter can be guaranteed. Be aware that the frequency characteristic may not be satisfied when this setting is altered. When altering this setting, always make sure that the OSC1 oscillator circuit is inactive. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 2-27 (Rev. 1.1)
Page 55 For the recommended pull-up resistor value, refer to “Recommended Operating Conditions, Debug pin pull-up re- sistors R ” in the “Electrical Characteristics” chapter. R and R are not required when using the debug DBG1–2 DBG1 DBG2 pins as general-purpose I/O port pins. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 56 Architecture Reference Manual ® 2. Cortex -M0+Technical Reference Manual ® 3. Cortex -M0+ Devices Generic User Guide ® These documents can be downloaded from the document site of Arm Ltd. https://developer.arm.com/documentation Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 57 Flash memory (1M bytes) (Device size: 32 bits) 0x0008 0000 0x0007 ffff Reserved 0x0006 0000 0x0005 ffff Flash area (384K bytes) (Device size: 32 bits) 0x0000 0000 Figure 4.1.1 Memory Map Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 58 Notes: • When programming the Flash memory, 2.2 V or more V voltage is required. • Be sure to avoid using the V pin output for driving external circuits. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 59 T16 Ch.0 Counter Data Register 0x4000 014a T16_0INTF T16 Ch.0 Interrupt Flag Register 0x4000 014c T16_0INTE T16 Ch.0 Interrupt Enable Register Flash controller (FLASHC) 0x4000 01b0 FLASHCWAIT FLASHC Flash Read Cycle Register Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 60 0x4000 027a PPORTP7CHATEN P7 Port Chattering Filter Enable Register 0x4000 027c PPORTP7MODSEL P7 Port Mode Select Register 0x4000 027e PPORTP7FNCSEL P7 Port Function Select Register 0x4000 0280 PPORTP8DAT P8 Port Data Register Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 61 I2C Ch.0 Clock Control Register 0x4000 03c2 I2C_0MOD I2C Ch.0 Mode Register 0x4000 03c4 I2C_0BR I2C Ch.0 Baud-Rate Register 0x4000 03c8 I2C_0OADR I2C Ch.0 Own Address Register 0x4000 03ca I2C_0CTL I2C Ch.0 Control Register Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 62 0x4000 0486 T16_3TR T16 Ch.3 Reload Data Register 0x4000 0488 T16_3TC T16 Ch.3 Counter Data Register 0x4000 048a T16_3INTF T16 Ch.3 Interrupt Flag Register 0x4000 048c T16_3INTE T16 Ch.3 Interrupt Enable Register Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 63 0x4000 06a0 QSPI_0FRLDMAEN QSPI Ch.0 FIFO Data Ready DMA Request Enable Register 0x4000 06a2 QSPI_0MMACFG1 QSPI Ch.0 Memory Mapped Access Configuration Register 1 0x4000 06a4 QSPI_0RMADRH QSPI Ch.0 Remapping Start Address High Register Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 64 0x4000 080a LCD32CDSP LCD32C Display Control Register 0x4000 080c LCD32CCOMC0 LCD32C COM Pin Control Register 0 0x4000 080e LCD32CCOMC1 LCD32C COM Pin Control Register 1 0x4000 0810 LCD32CINTF LCD32C Interrupt Flag Register Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 65 USB Debug RAM Data Register 0x4000 0970 USBMISCCTL USB Misc Control Register 0x4000 0974 USBMISCWRDMAEN USB FIFO Write DMA Request Enable Register 0x4000 0976 USBMISCRDDMAEN USB FIFO Read DMA Request Enable Register Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 66 4.7 Memory Mapped Access Area For External Flash Memory This area is used to read data from the external Flash memory via the quad synchronous serial interface. For more information, refer to the “Quad Synchronous Serial Interface” chapter. Seiko Epson Corporation 4-10 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 67 Notes: • Be sure to set the FLASHCWAIT.RDWAIT[1:0] bits before the system clock is configured. • When the FLASHCWAIT.RDWAIT[1:0] bit setting is altered from 0x2 to 0x1, add two NOP instructions immediately after that. Program example: FLASHC->WAIT_b.RDWAIT = 1; asm(“NOP”); asm(“NOP”); CLG->OSC_b.IOSCEN = 0; Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 4-11 (Rev. 1.1)
Page 68 • IOSC oscillation stabilization waiting completion • OSC1 oscillation stabilization waiting completion • OSC3 oscillation stabilization waiting completion • OSC1 oscillation stop • IOSC oscillation auto-trimming completion • IOSC oscillation auto-trimming error Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 69 • Transmit buﬀer empty VTOR + 0x80 IR remote controller • Compare AP interrupt • Compare DB VTOR + 0x84 LCD driver interrupt Frame VTOR + 0x88 16-bit timer Ch.3 interrupt Underﬂow Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 70 0 to 192 (a lower value has a higher priority). The priorities of reset, NMI, and HardFault are fixed at the predefined values. For more information, refer to the documents introduced in Section 3.4, such as “Cortex -M0+ Devices Generic User Guide.” ® Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 71 The watchdog timer embedded in this IC can generate a non-maskable interrupt (NMI). This interrupt takes prece- dence over other interrupts and is unconditionally accepted by the CPU. For detailed information on generating NMI, refer to the “Watchdog Timer” chapter. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 72 • Priority level for each channel is selectable from two levels. • DMA transfers are allowed even if the CPU is placed into HALT mode. Figure 6.1.1 shows the configuration of the DMAC. Table 6.1.1 DMAC Channel Configuration of S1C31W73 Item S1C31W73 Number of channels 4 channels (Ch.0 to Ch.3)
Page 73 256 bytes DMACCPTR.CPTR[31:0] (CPTR[7:0] = 0x00) DMACCPTR.CPTR[31:0] + 0x080 9 to 16 512 bytes DMACCPTR.CPTR[31:0] (CPTR[8:0] = 0x000) DMACCPTR.CPTR[31:0] + 0x100 17 to 32 1,024 bytes DMACCPTR.CPTR[31:0] (CPTR[9:0] = 0x000) DMACCPTR.CPTR[31:0] + 0x200 Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 74 6.4.2 Transfer Destination End Pointer Set the address to which the last transfer data is written. The address for writing transfer data should be set as it is if the transfer destination address is not incremented. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 75 When the DMAC is performing a successive transfer, it suspends the data transfer at the cycle set with R_pow- er. If DMA requests have been issued at that point, the DMAC re-arbitrates them according to their priorities and then performs a DMA transfer for the channel with the highest priority. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 76 DMA transfer 1 DMA transfer 2 DMA transfer 3 DMA transfer 4 DMA transfer 7 DMA transfer 8 operation DMACENDIF.ENDIFn DMA transfer request Figure 6.5.2.1 Auto-Request Transfer Operation Example (N = 8, 2 = 2) Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 77 5. Set cycle_ctrl to 0x0 after a DMA transfer completion interrupt has occurred by the next to last task. 6. The DMA transfer is completed when a DMA transfer completion interrupt occurs by the last task. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 78 Copy the data structure for Task D to the alternate data structure. (cycle_ctrl = 0x1, 2 = 4, N = 4) Task D DMA transfer completion interrupt Figure 6.5.4.2 Memory Scatter-Gather Transfer Operation Example Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 79 Copy the data structure for Task D to the alternate data structure. (cycle_ctrl = 0x1, 2 = 4, N = 4) Task D DMA transfer completion interrupt Figure 6.5.5.1 Peripheral Scatter-Gather Transfer Operation Example Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 80 The DMAC provides interrupt enable bits corresponding to each interrupt flag. An interrupt request is sent to the CPU only when the interrupt flag, of which interrupt has been enabled by the interrupt enable bit, is set. For more information on interrupt control, refer to the “Interrupt” chapter. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 81 – 15–8 – 0x00 – – 7–1 – 0x00 – MSTEN – – Bits 31–1 Reserved Bit 0 MSTEN This bit enables the DMA controller. 1 (W): Enable 0 (W): Disable Seiko Epson Corporation 6-10 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 82 DMA transfer requests from peripheral circuits have been disabled. 0 (R): DMA transfer requests from peripheral circuits have been enabled. Each bit corresponds to a DMAC channel. The high-order bits for the unimplemented channels are ineffective. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 6-11 (Rev. 1.1)
Page 83 The alternate data structure has been enabled. 0 (R): The primary data structure has been enabled. Each bit corresponds to a DMAC channel. The high-order bits for the unimplemented channels are ineffective. Seiko Epson Corporation 6-12 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 84 ERRIF This bit indicates the DMAC error interrupt cause occurrence status. 1 (R): Cause of interrupt occurred 0 (R): No cause of interrupt occurred 1 (W): Clear flag 0 (W): Ineffective Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 6-13 (Rev. 1.1)
Page 85 DMAC Error Interrupt Enable Set Register Register name Bit name Initial Reset Remarks DMACERRIESET 31–24 – 0x00 – – 23–16 – 0x00 – 15–8 – 0x00 – 7–1 – 0x00 – ERRIESET Bits 31–1 Reserved Seiko Epson Corporation 6-14 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 86 0x00 – ERRIECLR – – Bits 31–1 Reserved Bit 0 ERRIECLR This bit disables DMA error interrupts. 1 (W): Disable interrupt (The DMACERRIESET register is cleared to 0.) 0 (W): Ineffective Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 6-15 (Rev. 1.1)
Page 87 Note: ‘x’, which is used in the port names Pxy, register names, and bit names, refers to a port group (x = 0, 1, 2, ··· , d) and ‘y’ refers to a port number (y = 0, 1, 2, ··· , 7). Figure 7.1.1 shows the configuration of PPORT. Table 7.1.1 Port Configuration of S1C31W73 Item S1C31W73...
Page 88 Falling time (port level = high → low) [second] High level Schmitt input threshold voltage [V] Low level Schmitt input threshold voltage [V] : Pull-up/pull-down resistance [W] Pin capacitance [F] Parasitic capacitance on the board [F] BOARD Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 89 • Port pins: High impedance state • Port function: Configured to GPIO This status continues until the ports are configured via software. The debugging function ports are configured for debug signal input/output. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 90 * Steps 1 and 5 are required for the ports with an interrupt function. Step 2 is required for the ports with a chat- tering filter function. Table 7.4.1.1 lists the port status according to the combination of data input/output control and pull-up/down control. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 91 1. Configure the ports to be used for key-entry reset as general-purpose input ports (refer to “Initial settings when using a port as a general-purpose input port (only for the ports with GPIO function)”). 2. Configure the input pin combination for key-entry reset using the PPORTCLK.KRSTCFG[1:0] bits. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 92 These bits are used to set data to be output from the GPIO port pins. 1 (R/W): Output high level from the port pin 0 (R/W): Output low level from the port pin Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 93 PPORTPxIOEN.PxIENy bit is set and the port is not pulled up/down. These bits do not affect the pull-up/down control when the port is used as a peripheral I/O function. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 94 PPORTPxMODSEL 15–8 – 0x00 – – 7–0 PxSEL[7:0] 0x00 *1: The bit configuration differs depending on the port group. *2: The initial value may be changed by the port. Bits 15–8 Reserved Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 95 Table 7.6.2 Key-Entry Reset Function Settings PPORTCLK.KRSTCFG[1:0] bits key-entry reset Reset when P0[3:0] inputs = all low Reset when P0[2:0] inputs = all low Reset when P0[1:0] inputs = all low Disable Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 96 A port generated an interrupt 0 (R): No port generated an interrupt The PPORTINTFGRP.PxINT bit is cleared when the interrupt flag for the port that has generated an interrupt is cleared. Seiko Epson Corporation 7-10 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 97 RFC Ch.0 SENA0 UPMUX – – – – RFC Ch.0 REF0 UPMUX – – – – RFC Ch.0 RFIN0 UPMUX – – – – *1: Refer to the “Universal Port Multiplexer” chapter. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 7-11 (Rev. 1.1)
Page 98 – – REMC3 REMO UPMUX – – – – REMC3 CLPLS UPMUX – – – – RTCA RTC1S UPMUX – – – – *1: Refer to the “Universal Port Multiplexer” chapter. Seiko Epson Corporation 7-12 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 99 – QSPI Ch.0 #QSPISS0 UPMUX – – – – EXOSC UPMUX – – – – RFC Ch.0 RFCLKO0 UPMUX – – – – *1: Refer to the “Universal Port Multiplexer” chapter. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 7-13 (Rev. 1.1)
Page 100 – – – – UPMUX ADC12A ADIN05 – – – – UPMUX ADC12A ADIN06 – – – – UPMUX ADC12A VREFA0 – – *1: Refer to the “Universal Port Multiplexer” chapter. Seiko Epson Corporation 7-14 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 101 #ADTRG0 – – – – LCD32C LFRO – – – – – – – – – – SVD4 Ch.0 EXSVD00 – – – – – – SVD4 Ch.0 EXSVD01 – – Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 7-15 (Rev. 1.1)
Page 102 – LCD32C COM20/ SEG91 – – – – – – LCD32C COM21/ SEG90 – – – – – – LCD32C COM22/ SEG89 – – – – – – LCD32C COM23/ SEG88 Seiko Epson Corporation 7-16 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 103 – LCD32C COM28/ SEG83 – – – – – – LCD32C COM29/ SEG82 – – – – – – LCD32C COM30/ SEG81 – – – – – – LCD32C COM31/ SEG80 Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 7-17 (Rev. 1.1)
Page 104 – – – – – LCD32C SEG75 – – – – – – LCD32C SEG74 – – – – – – LCD32C SEG73 – – – – – – LCD32C SEG72 Seiko Epson Corporation 7-18 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 105 – – – – – LCD32C SEG67 – – – – – – LCD32C SEG66 – – – – – – LCD32C SEG65 – – – – – – LCD32C SEG64 Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 7-19 (Rev. 1.1)
Page 106 Peripheral Peripheral Peripheral Peripheral SWCLK – – – – – – – – – – – – – – – – OSC3 – – – – – – OSC4 – – Seiko Epson Corporation 7-20 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 107 Register) 7–4 CLKDIV[3:0] R/WP 3–2 KRSTCFG[1:0] R/WP 1–0 CLKSRC[1:0] R/WP PPORTINTFGRP 15–9 – 0x00 – – (P Port Interrupt Flag P8INT Group Register) P7INT P6INT P5INT P4INT P3INT P2INT P1INT P0INT Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 7-21 (Rev. 1.1)
Page 108 4. Initialize the peripheral circuit. 5. Set the PPORTPxFNCSEL.PxyMUX[1:0] bits of the I/O port to 0x1. (Select peripheral I/O function 1) 6. Set the PPORTPxMODSEL.PxSELy bit of the I/O port to 1. (Enable peripheral I/O function) Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 109 Note: Do not assign a peripheral input function to two or more I/O ports. Although the I/O ports output the same waveforms when an output function is assigned to two or more I/O port, a skew oc- curs due to the internal delay. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 110 CLK_WDT2 supply is suspended, the register retains the status before DEBUG mode was entered. If the WDT2CLK.DBRUN bit = 1, the CLK_WDT2 supply is not suspended and WDT2 will keep operating in DEBUG mode. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 111 1. Write 0x0096 to the SYSPROT.PROT[15:0] bits. (Remove system protection) 2. Write 0xa to the WDT2CTL.WDTRUN[3:0] bits. (Stop WDT2) 3. Write a value other than 0x0096 to the SYSPROT.PROT[15:0] bits. (Set system protection) Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 112 IOSC OSC1 OSC3 EXOSC 1/65,536 1/128 1/65,536 1/32,768 1/32,768 1/16,384 1/16,384 1/8,192 1/8,192 (Note) The oscillation circuits/external input that are not supported in this IC cannot be selected as the clock source. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 113 Always 0x0 is read if a value other than 0xa is written. Since an NMI or reset may be generated immediately after running depending on the counter value, WDT2 should also be reset concurrently when running WDT2. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 114 These bits set the NMI/reset generation cycle. The value set in this register is compared with the 10-bit counter value while WDT2 is running, and an NMI or reset is generated when they are matched. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 115 If the port is shared with the RTCA output function and other functions, the RTCA function must be assigned to the port. For more information, refer to the “I/O Ports” chapter. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 10-1 (Rev. 1.1)
Page 116 · · · · · · · · · · · · 0x3e 59.1 0x7e -1.9 0x3f 60.1 0x7f -1.0 Minimum resolution: 1 ppm, Correction rate range: -61.0 to 60.1 ppm Seiko Epson Corporation 10-2 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 117 3. Write 1 to the RTCAINTF.ALARMIF bit to clear the alarm interrupt flag. 4. Write 1 to the RTCAINTE.ALARMIE bit to enable alarm interrupts. When the real-time clock counter reaches the alarm time set in Step 2, an alarm interrupt occurs. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 10-3 (Rev. 1.1)
Page 118 The stopwatch consists of 1/100-second and 1/10-second counters and these counters perform counting up in incre- ments of approximate 1/100 and 1/10 seconds with the count-up patterns shown in Figure 10.4.4.1. Seiko Epson Corporation 10-4 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 119 1 Hz counter value. • An alarm interrupt occurs after a lapse of 1/256 second from matching between the AM/PM (in 12H mode), hour, minute, and second counter value and the alarm setting value. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 10-5 (Rev. 1.1)
Page 120 This bit executes the 30-second correction time adjustment function. 1 (W): Execute 30-second correction 0 (W): Ineffective 1 (R): 30-second correction is executing. 0 (R): 30-second correction has finished. (Normal operation) Seiko Epson Corporation 10-6 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 121 1 as well. However, no correcting operation is performed. RTCA Second Alarm Register Register name Bit name Initial Reset Remarks RTCAALM1 – – – 14–12 RTCSHA[2:0] 11–8 RTCSLA[3:0] 7–0 – 0x00 – Bit 15 Reserved Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 10-7 (Rev. 1.1)
Page 122 BCD code. RTCA Stopwatch Control Register Register name Bit name Initial Reset Remarks RTCASWCTL 15–12 BCD10[3:0] – 11–8 BCD100[3:0] 7–5 – – SWRST Read as 0. 3–1 – – – SWRUN Seiko Epson Corporation 10-8 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 123 10-second digit and the 1-second digit of the second counter, respectively. The setting/read values are a BCD code within the range from 0 to 59. Note: Be sure to avoid writing to the RTCASEC.RTCSH[2:0]/RTCSL[3:0] bits while the RTCACTLL. RTCBSY bit = 1. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 10-9 (Rev. 1.1)
Page 124 1 to 12 in 12H mode or 0 to 23 in 24H mode. Note: Be sure to avoid writing to the RTCAHUR.RTCHH[1:0]/RTCHL[3:0] bits while the RTCACTLL. RTCBSY bit = 1. Bit 7 Reserved Seiko Epson Corporation 10-10 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 125 The day of the week counter is a base-7 counter and the setting/read values are 0x0 to 0x6. Table 10.6.2 lists the correspondence between the count value and day of the week. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 10-11 (Rev. 1.1)
Page 126 The following shows the correspondence between the bit and interrupt: RTCAINTF.RTCTRMIF bit: Theoretical regulation completion interrupt RTCAINTF.SW1IF bit: Stopwatch 1 Hz interrupt RTCAINTF.SW10IF bit: Stopwatch 10 Hz interrupt RTCAINTF.SW100IF bit: Stopwatch 100 Hz interrupt Bits 11–9 Reserved Seiko Epson Corporation 10-12 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 127 The following shows the correspondence between the bit and interrupt: RTCAINTE.RTCTRMIE bit: Theoretical regulation completion interrupt RTCAINTE.SW1IE bit: Stopwatch 1 Hz interrupt RTCAINTE.SW10IE bit: Stopwatch 10 Hz interrupt RTCAINTE.SW100IE bit: Stopwatch 100 Hz interrupt Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 10-13 (Rev. 1.1)
Page 128 RTCAINTE.T1DAYIE bit: 1-day interrupt RTCAINTE.T1HURIE bit: 1-hour interrupt RTCAINTE.T1MINIE bit: 1-minute interrupt RTCAINTE.T1SECIE bit: 1-second interrupt RTCAINTE.T1_2SECIE bit: 1/2-second interrupt RTCAINTE.T1_4SECIE bit: 1/4-second interrupt RTCAINTE.T1_8SECIE bit: 1/8-second interrupt RTCAINTE.T1_32SECIE bit: 1/32-second interrupt Seiko Epson Corporation 10-14 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 129 - Continuous operation is also possible. Figure 11.1.1 shows the configuration of SVD4. Table 11.1.1 SVD4 Configuration of S1C31W73 Item S1C31W73 Number of channels 1 channel (Ch.0)
Page 130 SLEEP mode and SVD4 Ch.n stops with the register settings maintained at those before entering SLEEP mode. After the CPU returns to normal mode, CLK_SVD4_n is supplied and the SVD4 Ch.n operation resumes. Seiko Epson Corporation 11-2 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 131 SVD4_nCTL.MODEN bit = 1, wait for at least SVD circuit re- SVD_EXT sponse time before reading the SVD4_nINTF.SVDDT bit (refer to “Supply Voltage Detector Characteristics, SVD circuit response time t ” in the “Electrical Characteristics” chapter). Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 11-3 (Rev. 1.1)
Page 132 An interrupt request is sent to the CPU only when the SVD4_nINTF.SVDIF bit is set while the interrupt is enabled by the SVD4_nINTE.SVDIE bit. For more information on interrupt control, refer to the “Inter- rupt” chapter. Seiko Epson Corporation 11-4 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 133 Reserved Bits 6–4 CLKDIV[2:0] These bits select the division ratio of the SVD4 Ch.n operating clock. Bits 3–2 Reserved Bits 1–0 CLKSRC[1:0] These bits select the clock source of SVD4 Ch.n. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 11-5 (Rev. 1.1)
Page 134 0x01 ↓ 0x00 For the configurable range and voltage values, refer to “Supply Voltage Detector Characteristics, SVD detection voltage V /EXSVD detection voltage V ” in the “Electrical Characteristics” chapter. SVD_EXT Seiko Epson Corporation 11-6 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 135 , EXSVDnx) < SVD detection voltage V or EXSVD detection voltage V SVD_EXT 0 (R): Power supply voltage (V , EXSVDnx) ≥ SVD detection voltage V or EXSVD detection voltage V SVD_EXT Bits 7–1 Reserved Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 11-7 (Rev. 1.1)
Page 136 • To prevent generating unnecessary interrupts, the corresponding interrupt flag should be cleared before enabling interrupts. Seiko Epson Corporation 11-8 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 137 • A clock source and clock division ratio for generating the count clock are selectable. • Repeat mode or one-shot mode is selectable. • Can generate counter underflow interrupts. Figure 12.1.1 shows the configuration of a T16 channel. Table 12.1.1 T16 Channel Configuration of S1C31W73 Item S1C31W73 Number of channels 8 channels (Ch.0–Ch.7)
Page 138 (Set reload data (counter preset data)) 5. Set the following bits when using the interrupt: - Write 1 to the T16_nINTF.UFIF bit. (Clear interrupt flag) - Set the T16_nINTE.UFIE bit to 1. (Enable underflow interrupt) Seiko Epson Corporation 12-2 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 139 At the same time the counter stops, the T16_ nCTL.PRUN bit is cleared automatically. Select this mode to stop the counter after an interrupt has occurred once, such as for checking a specific lapse of time. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 12-3 (Rev. 1.1)
Page 140 Bits 7–4 CLKDIV[3:0] These bits select the division ratio of the T16 Ch.n operating clock (counter clock). Bits 3–2 Reserved Bits 1–0 CLKSRC[1:0] These bits select the clock source of T16 Ch.n. Seiko Epson Corporation 12-4 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 141 PRESET MODEN Bits 15–9 Reserved Bit 8 PRUN This bit starts/stops the timer. 1 (W): Start timer 0 (W): Stop timer 1 (R): Timer is running 0 (R): Timer is idle Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 12-5 (Rev. 1.1)
Page 142 This bit indicates the T16 Ch.n underflow interrupt cause occurrence status. 1 (R): Cause of interrupt occurred 0 (R): No cause of interrupt occurred 1 (W): Clear flag 0 (W): Ineffective Seiko Epson Corporation 12-6 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 143 This bit enables T16 Ch.n underflow interrupts. 1 (R/W): Enable interrupts 0 (R/W): Disable interrupts Note: To prevent generating unnecessary interrupts, the corresponding interrupt flag should be cleared before enabling interrupts. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 12-7 (Rev. 1.1)
Page 144 • Input pin can be pulled up with an internal resistor. • The output pin is configurable as an open-drain output. • Provides the carrier modulation output function. Figure 13.1.1 shows the UART3 configuration. Table 13.1.1 UART3 Channel Configuration of S1C31W73 Item S1C31W73 Number of channels 2 channels (Ch.0 and Ch.1)
Page 145 (Clock source selection) - UART3_nCLK.CLKDIV[1:0] bits (Clock division ratio selection = Clock frequency setting) The UART3 operating clock should be selected so that the baud rate generator will be configured easily. Seiko Epson Corporation 13-2 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 146 (UART3_nMOD.STPB bit = 1). Parity function The parity function is configured using the UART3_nMOD.PREN and UART3_nMOD.PRMD bits. Table 13.4.1 Parity Function Setting UART3_nMOD.PREN bit UART3_nMOD.PRMD bit Parity function Odd parity Even parity Non parity Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 13-3 (Rev. 1.1)
Page 147 8. Configure the DMA controller and set the following UART3 control bits when using DMA transfer: - Write 1 to the DMA transfer request enable bits in the UART3_nTBEDMAEN and UART3_nRB1FDMAEN registers. (Enable DMA transfer requests) Seiko Epson Corporation 13-4 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 148 Read the UART3_nINTF.TBEIF bit UART3_nINTF.TBEIF = 1 ? Write transmit data to the UART3_nTXD register Transmit data remained? Wait for an interrupt request (UART3_nINTF.TBEIF = 1) Figure 13.5.2.2 Data Transmission Flowchart Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 13-5 (Rev. 1.1)
Page 149 UART3_nINTF.RB1FIF bit to 1 (receive buffer one byte full). If the sec- ond data is received without reading the first data, the UART3_nINTF.RB2FIF bit is set to 1 (receive buffer two bytes full). Seiko Epson Corporation 13-6 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 150 Set the UART3_nMOD.IRMD bit to 1 to use the IrDA interface. Data transfer control is identical to that for normal interface even if the IrDA interface function is enabled. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 13-7 (Rev. 1.1)
Page 151 CAREN = 0 CAREN = 1 USOUTn PECAR = 0 (INVTX = 1) CAREN = 1 PECAR = 1 Figure 13.5.5.1 Carrier Modulation Waveform (UART3_nMOD.CHLN = 1, UART3_nMOD.STPB = 0, UART3_nMOD.PREN = 1) Seiko Epson Corporation 13-8 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 152 When an overrun error occurs, the UART3_nINTF.OEIF bit (overrun error interrupt flag) is set to 1. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 13-9 (Rev. 1.1)
Page 153 After a DMA transfer has completed, disable the DMA transfer to prevent unintended DMA transfer requests from being issued. For more information on the DMA control, refer to the “DMA Controller” chapter. Seiko Epson Corporation 13-10 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 154 UART3 Ch.n Mode Register Register name Bit name Initial Reset Remarks UART3_nMOD 15–13 – – – PECAR CAREN BRDIV INVRX INVTX – – PUEN OUTMD IRMD CHLN PREN PRMD STPB Bits 15–13 Reserved Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 13-11 (Rev. 1.1)
Page 155 1 (R/W): Enable parity function 0 (R/W): Disable parity function Bit 1 PRMD This bit selects either odd parity or even parity when using the parity function. 1 (R/W): Odd parity 0 (R/W): Even parity Seiko Epson Corporation 13-12 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 156 Note: If the UART3_nCTL.MODEN bit is altered from 1 to 0 while sending/receiving data, the data being sent/received cannot be guaranteed. When setting the UART3_nCTL.MODEN bit to 1 again after that, be sure to write 1 to the UART3_nCTL.SFTRST bit as well. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 13-13 (Rev. 1.1)
Page 157 This bit indicates the receiving status. (See Figure 13.5.3.1.) 1 (R): During receiving 0 (R): Idle Bit 8 TBSY This bit indicates the sending status. (See Figure 13.5.2.1.) 1 (R): During sending 0 (R): Idle Bit 7 Reserved Seiko Epson Corporation 13-14 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 158 UART3_nINTE.PEIE bit: Parity error interrupt UART3_nINTE.OEIE bit: Overrun error interrupt UART3_nINTE.RB2FIE bit: Receive buffer two bytes full interrupt UART3_nINTE.RB1FIE bit: Receive buffer one byte full interrupt UART3_nINTE.TBEIE bit: Transmit buffer empty interrupt Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 13-15 (Rev. 1.1)
Page 159 UART3_nCAWF 15–8 – 0x00 – – 7–0 CRPER[7:0] 0x00 Bits 15–8 Reserved Bits 7–0 CRPER[7:0] These bits set the carrier modulation output frequency. For more information, refer to “Carrier Modu- lation.” Seiko Epson Corporation 13-16 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 160 • Slave mode is capable of being operated in SLEEP mode allowing wake-up by an SPIA interrupt. • Input pins can be pulled up/down with an internal resistor. Figure 14.1.1 shows the SPIA configuration. Table 14.1.1 SPIA Channel Configuration of S1C31W73 Item S1C31W73 Number of channels 2 channels (Ch.0 and Ch.1)
Page 161 SDIn #SPISS0 SPICLKn #SPISS1 #SPISS #SPISS2 External SPI master device External SPI slave devices SPICLK SPICLK #SPISS SPICLK Figure 14.2.2.2 Connections between SPIA in Slave Mode and External SPI Master Device Seiko Epson Corporation 14-2 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 162 16-bit timer channel and converts it to the SPICLKn. The 16-bit timer must be run with an appro- priate reload data set. The SPICLKn frequency (baud rate) and the 16-bit timer reload data are calculated by the equations shown below. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 14-3 (Rev. 1.1)
Page 163 SDIn SDOn (Master mode) SDOn (Slave mode) SDOn (Slave mode) Writing data to the SPIA_nTXD register Figure 14.3.3.1 SPI Clock Phase and Polarity (SPIA_nMOD.LSBFST bit = 0, SPIA_nMOD.CHLN[3:0] bits = 0x7) Seiko Epson Corporation 14-4 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 164 6. Configure the DMA controller and set the following SPIA control bits when using DMA transfer: - Write 1 to the DMA transfer request enable bits in the SPIA_nTBEDMAEN and SPIA_nRBFDMAEN registers. (Enable DMA transfer requests) Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 14-5 (Rev. 1.1)
Page 165 Data (W) → SPIA_nTXD Data (W) → SPIA_nTXD Software operations Data (W) → SPIA_nTXD 1 (W) → SPIA_nINTF.TENDIF Figure 14.5.2.1 Example of Data Sending Operations in Master Mode (SPIA_nMOD.CHLN[3:0] bits = 0x7) Seiko Epson Corporation 14-6 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 166 Transfer destination SPIA_nTXD register address Control data dst_inc 0x3 (no increment) dst_size 0x1 (haflword) src_inc 0x1 (+2) src_size 0x1 (halfword) R_power 0x0 (arbitrated for every transfer) n_minus_1 Number of transfer data cycle_ctrl 0x1 (basic transfer) Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 14-7 (Rev. 1.1)
Page 167 Software operations SPIA_nRXD → Data (R) Data (W) → SPIA_nTXD SPIA_nRXD → Data (R) 1 (W) → SPIA_nINTF.TENDIF Figure 14.5.3.1 Example of Data Receiving Operations in Master Mode (SPIA_nMOD.CHLN[3:0] bits = 0x7) Seiko Epson Corporation 14-8 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 168 Control data dst_inc 0x3 (no increment) dst_size 0x1 (haflword) src_inc 0x3 (no increment) src_size 0x1 (halfword) R_power 0x0 (arbitrated for every transfer) n_minus_1 Number of transfer data cycle_ctrl 0x1 (basic transfer) Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 14-9 (Rev. 1.1)
Page 169 Writing transmit data is not a trigger to start data transfer. Therefore, it is not necessary to write dummy data to the transmit data buffer when performing data reception only. Seiko Epson Corporation 14-10 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 170 1. Wait for an end-of-transmission interrupt (SPIA_nINTF.TENDIF bit = 1). Or determine end of transfer via the received data. 2. Set the SPIA_nCTL.MODEN bit to 0 to disable the SPIA Ch.n operations. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 14-11 (Rev. 1.1)
Page 171 SPIA_nINTF.BSY SPIA_nMOD register CPOL bit CPHA bit SPICLKn SDOn SPICLKn SDOn SPIA_nINTF.TENDIF Writing data to the SPIA_nTXD register Figure 14.6.1 SPIA_nINTF.BSY and SPIA_nINTF.TENDIF Bit Set Timings (when SPIA_nMOD.CHLN[3:0] bits = 0x7) Seiko Epson Corporation 14-12 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 172 16 bits 15 bits 14 bits 13 bits 12 bits 11 bits 10 bits 9 bits 8 bits 7 bits 6 bits 5 bits 4 bits 3 bits 2 bits Setting prohibited Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 14-13 (Rev. 1.1)
Page 173 Note: If the SPIA_nCTL.MODEN bit is altered from 1 to 0 while sending/receiving data, the data being sent/received cannot be guaranteed. When setting the SPIA_nCTL.MODEN bit to 1 again after that, be sure to write 1 to the SPIA_nCTL.SFTRST bit as well. Seiko Epson Corporation 14-14 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 174 These bits indicate the SPIA interrupt cause occurrence status. 1 (R): Cause of interrupt occurred 0 (R): No cause of interrupt occurred 1 (W): Clear flag (OEIF, TENDIF) 0 (W): Ineffective Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 14-15 (Rev. 1.1)
Page 175 Ch.15) when a receive buffer full state has occurred. 1 (R/W): Enable DMA transfer request 0 (R/W): Disable DMA transfer request Each bit corresponds to a DMA controller channel. The high-order bits for the unimplemented chan- nels are ineffective. Seiko Epson Corporation 14-16 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 176 • Can issue a DMA transfer request when a receive buffer full, a transmit buffer empty, or a memory mapped ac- cess (32-bit read) occurs. Figure 15.1.1 shows the QSPI configuration. Table 15.1.1 QSPI Channel Configuration of S1C31W73 Item S1C31W73 Number of channels 1 channel (Ch.0)
Page 177 In this case, GPIO pins other than #QSPISSn can also be used as the slave select output ports to connect the QSPI to more than one external QSPI device. Figures 15.2.2.1 to 15.2.2.7 show connection diagrams between the QSPI in each mode and external QSPI devices. Seiko Epson Corporation 15-2 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 178 External dual-I/O SPI slave devices QSDIOn0 SDIO0 QSPICLKn SPICK #SPISS SDIO1 SDIO0 SPICK Figure 15.2.2.3 Connections between QSPI in Register Access Master Mode and External Dual-I/O SPI Slave Devices Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 15-3 (Rev. 1.1)
Page 179 #SPISS2 External single-I/O SPI master device SPICK SPICK External single-I/O SPI slave devices #SPISS SPICK Figure 15.2.2.5 Connections between QSPI in Slave Mode and External Single-I/O SPI (Legacy SPI) Master Device Seiko Epson Corporation 15-4 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 180 QSDIO2 QSDIO2 QSDIO1 QSDIO1 QSDIO0 QSDIO0 QSPICLK QSPICLK External QSPI slave devices #QSPISS QSDIO3 QSDIO2 QSDIO1 QSDIO0 QSPICLK Figure 15.2.2.7 Connections between QSPI in Slave Mode and External QSPI Master Device Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 15-5 (Rev. 1.1)
Page 181 To supply CLK_QSPIn to the QSPI, the 16-bit timer clock source must be enabled in the clock generator. It does not matter how the T16_mCTL.MODEN and T16_mCTL.PRUN bits of the corresponding 16-bit timer channel are set (1 or 0). Seiko Epson Corporation 15-6 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 182 (Master mode, output) QSDIOn (Slave mode, output) QSDIOn (Slave mode, output) QSDIOn Writing data to the QSPI_nTXD register Figure 15.3.3.1 QSPI Clock Phase and Polarity (QSPI_nMOD.LSBFST bit = 0, QSPI_nMOD.CHLN[3:0] bits = 0x7) Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 15-7 (Rev. 1.1)
Page 183 Figure 15.4.2 Data Format Selection for Dual Transfer Mode Using the QSPI_nMOD.LSBFST Bit (QSPI_nMOD.TMOD[1:0] bits = 0x1, QSPI_nMOD.CHDL[3:0] bits = 0x7, QSPI_nMOD.CHLN[3:0] bits = 0x7, QSPI_nMOD.CPOL bit = 0, QSPI_nMOD.CPHA bit = 0) Seiko Epson Corporation 15-8 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 184 (QSPI_nCTL.DIR bit = 1). The number of data transfer clocks is configured with the QSPI_nMOD. CHLN[3:0] bits. Since four data lines are used for data transfer, the data bit length (number of clocks) is obtained by dividing the number of transfer data bits by four. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 15-9 (Rev. 1.1)
Page 185 The QSPI treats the data cycle as 2 cycles including 2 driving cycles. (QSPI_nMOD.CHDL[3:0] bits = 0x1, QSPI_nMOD.CHLN[3:0] bits = 0x1) Figure 15.5.2.1 XIP Example - Spansion S25FL128S Quad I/O Read Command Sequence (3-byte address, 0xeb [ExtAdd = 0], LC = 0b00) Seiko Epson Corporation 15-10 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 186 - QSPI_nMOD.NOCLKDIV bit (Select master mode operating clock) - QSPI_nMOD.LSBFST bit (Select MSB first/LSB first) - QSPI_nMOD.CPHA bit (Select clock phase) - QSPI_nMOD.CPOL bit (Select clock polarity) - QSPI_nMOD.MST bit (Select master/slave mode) Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 15-11 (Rev. 1.1)
Page 187 Even if the clock is being output from the QSPICLKn pin, the next transmit data can be written to the QSPI_ nTXD register after making sure the QSPI_nINTF.TBEIF bit is set to 1. Seiko Epson Corporation 15-12 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 188 DMA transfer in advance so that transmit data will be transferred to the QSPI_nTXD register. For more information on DMA, refer to the “DMA Controller” chapter. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 15-13 (Rev. 1.1)
Page 189 TMOD[1:0] bits is received when the QSPI_nINTF.RBFIF bit is set to 1, the QSPI_nRXD register is overwritten with the newly received data and the previously received data is lost. In this case, the QSPI_nINTF.OEIF bit is set. Seiko Epson Corporation 15-14 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 190 DMA controller and dummy data is transferred from the specified memory to the QSPI_ nTXD register via DMA Ch.x when the QSPI_nINTF.TBEIF bit is set to 1 (transmit buffer empty). Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 15-15 (Rev. 1.1)
Page 191 DMA controller transfers data from the QSPI_nRXD register and then writes another dummy byte to the QSPI_nTXD register, allowing the QSPI to read the next data. 13. Wait for a DMA interrupt. Seiko Epson Corporation 15-16 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 192 If the address in the memory mapped access area that is continuous to the previous read address is read when the FIFO contains the prefetched data (FIFO data ready status), the prefetched data is sent to the internal system bus with the HREADY signal held high (zero-wait read). Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 15-17 (Rev. 1.1)
Page 193 Data cycle 3 QSPI_nMOD register Dummy cycle Data cycle 1 (prefetching) (prefetching) CPOL bit CPHA bit QSPICLKn QSDIOn[3:0] Figure 15.5.6.1 Data Receiving Operation in Memory Mapped Access Mode - First 32-bit Read Seiko Epson Corporation 15-18 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 194 HRDATA fifo_read_level Data cycle Data cycle QSPI_nMOD register (for n+8) (prefetching) CPOL bit CPHA bit QSPICLKn QSDIOn[3:0] Figure 15.5.6.2 Data Receiving Operation in Memory Mapped Access Mode - 32-bit Sequential Read Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 15-19 (Rev. 1.1)
Page 195 Dummy cycle (low-order 16 bits) (for n) (for n+8) QSPI_nMOD register #QSPISSn CPOL bit CPHA bit QSPICLKn QSDIOn[3:0] Figure 15.5.6.3 Data Receiving Operation in Memory Mapped Access Mode - 32-bit Non-Sequential Read Seiko Epson Corporation 15-20 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 196 HADDR HTRANS HSIZE HREADY HRDATA QSPI_nMOD register Dummy cycle Data cycle CPOL bit CPHA bit QSPICLKn QSDIOn[3:0] Figure 15.5.6.4 Data Receiving Operation in Memory Mapped Access Mode - First 8/16-bit Read Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 15-21 (Rev. 1.1)
Page 197 HCLK HSEL HADDR HTRANS HSIZE HREADY HRDATA QSPI_nMOD register Data cycle CPOL bit CPHA bit QSPICLKn QSDIOn[3:0] Figure 15.5.6.5 Data Receiving Operation in Memory Mapped Access Mode - 8/16-bit Sequential Read Seiko Epson Corporation 15-22 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 198 Address cycle Dummy cycle Data cycle (low-order 16 bits) QSPI_nMOD register #QSPISSn CPOL bit CPHA bit QSPICLKn QSDIOn[3:0] Figure 15.5.6.6 Data Receiving Operation in Memory Mapped Access Mode - 8/16-bit Non-Sequential Read Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 15-23 (Rev. 1.1)
Page 199 The transfer source/destination and control data must be set for the DMA controller and the relevant DMA channel must be enabled to start a DMA transfer in advance. For more information on DMA, refer to the “DMA Controller” chapter. Seiko Epson Corporation 15-24 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 200 1. Wait for an end-of-transmission interrupt (QSPI_nINTF.TENDIF bit = 1). 2. Set the QSPI_nCTL.MODEN bit to 0 to disable the QSPI Ch.n operations. 3. Stop the 16-bit timer to disable the clock supply to QSPI Ch.n. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 15-25 (Rev. 1.1)
Page 201 Data (W) → QSPI_nTXD Software operations QSPI_nRXD → Data (R) QSPI_nRXD → Data (R) Figure 15.5.9.1 Example of Data Transfer Operations in Slave Mode (QSPI_nMOD.CHDL[3:0] bits = QSPI_nMOD.CHLN[3:0] bits = 0x3) Seiko Epson Corporation 15-26 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 202 The QSPI_nINTF register also contains the BSY and MMABSY bits that indicate the QSPI operating status in reg- ister access and memory mapped access modes, respectively. Figure 15.6.1 shows the QSPI_nINTF.BSY, QSPI_ nINTF.MMABSY and QSPI_nINTF.TENDIF bit set timings. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 15-27 (Rev. 1.1)
Page 203 When a 32-bit data is prefetched into the FIFO When the FIFO read access FIFO data FIFO data ready flag in memory mapped access mode level is cleared to 0 ready (internal signal) Seiko Epson Corporation 15-28 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 204 Note: When using the QSPI in slave mode, the QSPI_nMOD.CHDL[3:0] bits should be set to the same value as the QSPI_nMOD.CHLN[3:0] bits. Bits 11–8 CHLN[3:0] These bits set the number of clocks for data transfer. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 15-29 (Rev. 1.1)
Page 205 0 (R/W): MSB first Bit 2 CPHA Bit 1 CPOL These bits set the QSPI clock phase and polarity. For more information, refer to “QSPI Clock (QSPI- CLKn) Phase and Polarity.” Seiko Epson Corporation 15-30 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 206 Note: If the QSPI_nCTL.MODEN bit is altered from 1 to 0 while sending/receiving data, the data being sent/received cannot be guaranteed. When setting the QSPI_nCTL.MODEN bit to 1 again after that, be sure to write 1 to the QSPI_nCTL.SFTRST bit as well. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 15-31 (Rev. 1.1)
Page 207 Transmit/receive busy 0 (R): Idle Bit 6 MMABSY This bit indicates the QSPI memory mapped access operating status. 1 (R): Memory mapped access state machine busy 0 (R): Idle Bits 5–4 Reserved Seiko Epson Corporation 15-32 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 208 Ch.15) when a transmit buffer empty state has occurred. 1 (R/W): Enable DMA transfer request 0 (R/W): Disable DMA transfer request Each bit corresponds to a DMA controller channel. The high-order bits for the unimplemented chan- nels are ineffective. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 15-33 (Rev. 1.1)
Page 209 11 clocks 10 clocks 9 clocks 8 clocks 7 clocks 6 clocks 5 clocks 4 clocks 3 clocks 2 clocks 1 clock Note: These bits specify a number of system clocks. Seiko Epson Corporation 15-34 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 210 Flash memory in the memory mapped access mode. This setting is re- quired to output the XIP confirmation bit to Micron Flash memories or to output the mode byte to Spansion Flash memories. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 15-35 (Rev. 1.1)
Page 211 The QSDIOn[3:0] pins are used. Dual transfer mode The QSDIOn[1:0] pins are used. The QSDIOn[3:2] pins are not used. Single transfer mode The QSDIOn[1:0] pins are used. The QSDIOn[3:2] pins are not used. Seiko Epson Corporation 15-36 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 212 Note: In memory mapped access mode, the mode byte is always output from the LSB first. When us- ing a Flash memory that expects the mode byte to be output from the MSB first, write the mode byte to this register in reverse bit order. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 15-37 (Rev. 1.1)
Page 213 • The input filter for the SDA and SCL inputs does not comply with the standard for removing noise spikes less than 50 ns. Figure 16.1.1 shows the I2C configuration. Table 16.1.1 I2C Channel Configuration of S1C31W73 Item S1C31W73 Number of channels 2 channels (Ch.0 and Ch.1)
Page 214 • The internal pull-up resistors for the I/O ports cannot be used for pulling up SDA and SCL. • When the I2C is set into master mode, no other master device can be connected to the I bus. Seiko Epson Corporation 16-2 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 215 16.3.3.1). Note: The I C bus transfer rate is limited to 100 kbit/s in standard mode or 400 kbit/s in fast mode. Do not set a transfer rate exceeding the limit. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 16-3 (Rev. 1.1)
Page 216 - Set the I2C_nCTL.MST bit to 0. (Set slave mode) - Set the I2C_nCTL.SFTRST bit to 1. (Execute software reset) - Set the I2C_nCTL.MODEN bit to 1. (Enable I2C Ch.n operations) Seiko Epson Corporation 16-4 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 217 I2C_nINTF.NACKIF bit = 1 (NACK received), the I2C Ch.n generates a repeated START condi- tion. When the repeated START condition has been generated, the I2C_nINTF.STARTIF and I2C_nINTF. TBEIF bits are both set to 1 same as when a START condition has been generated. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 16-5 (Rev. 1.1)
Page 218 Last data sent? Retry? Write 1 to the I2C_nCTL.TXSTOP bit Write data to the I2C_nTXD register Wait for an interrupt request (I2C_nINTF.STOPIF = 1) Figure 16.4.2.2 Master Mode Data Transmission Flowchart Seiko Epson Corporation 16-6 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 219 10. (When DMA is not used) Repeat Steps 6 to 8 until the end of data reception. 11. Wait for a STOP condition interrupt (I2C_nINTF.STOPIF bit = 1). Clear the I2C_nINTF.STOPIF bit by writing 1 after the interrupt has occurred. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 16-7 (Rev. 1.1)
Page 220 S: START condition, Sr: Repeated START condition, P: STOP condition, A: ACK, A: NACK, Saddr/R: Slave address + R(1), Data n: 8-bit data Figure 16.4.3.1 Example of Data Receiving Operations in Master Mode Seiko Epson Corporation 16-8 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 221 Transfer destination Memory address to which the last received data is stored Control data dst_inc 0x0 (+1) dst_size 0x0 (byte) src_inc 0x3 (no increment) src_size 0x0 (byte) R_power 0x0 (arbitrated for every transfer) n_minus_1 Number of receive data cycle_ctrl 0x1 (basic transfer) Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 16-9 (Rev. 1.1)
Page 222 Clear the I2C_nINTF.STARTIF bit by writing 1 after the interrupt has occurred. 9. Write the first address to the I2C_nTXD.TXD[7:1] bits and 1 that represents READ as the data transfer di- rection to the I2C_nTXD.TXD0 bit. 10. Perform data reception. Seiko Epson Corporation 16-10 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 223 Go to Step 6 when a STOP condition interrupt has occurred. ii. Go to Step 2 when a START condition interrupt has occurred. 6. Clear the I2C_nINTF.STOPIF bit and then terminate data sending operations. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 16-11 (Rev. 1.1)
Page 224 A: ACK, A: NACK, Saddr/R: Slave address + R(1), Saddr/W: Slave address + W(0), STARTIF = 1 Data n: 8-bit data Figure 16.4.5.1 Example of Data Sending Operations in Slave Mode Seiko Epson Corporation 16-12 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 225 I2C Ch.n sends an ACK and pulls down SCL to low. The received data in the shift register is transferred to the receive data buffer and the I2C_nINTF.RBFIF and I2C_nINTF.BYTEENDIF bits are both set to 1. After that, the received data can be read out from the I2C_nRXD register. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 16-13 (Rev. 1.1)
Page 226 Wait for an interrupt request (I2C_nINTF.RBFIF = 1) Last data received next? Write 1 to the I2C_nCTL.TXNACK bit Read receive data from the I2C_nRXD register Last data received? Figure 16.4.6.2 Slave Mode Data Reception Flowchart Seiko Epson Corporation 16-14 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 227 If SDA does not change from low when the I2C Ch.n outputs the ninth clock, it is regarded as an automatic bus clearing failure. In this case, the I2C Ch.n clears the I2C_nCTL.TXSTART bit to 0 and sets both the I2C_nINTF. ERRIF and I2C_nINTF.STARTIF bits to 1. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 16-15 (Rev. 1.1)
Page 228 4 <Master mode only> When 1 is written to the I2C_nCTL. I2C_nINTF.ERRIF = 1 TXSTART bit while the I2C_nINTF.BSY bit = 0 (Refer to “Au- Automatic bus clearing I2C_nCTL.TXSTART = 0 tomatic Bus Clearing Operation.”) failure I2C_nINTF.STARTIF = 1 Seiko Epson Corporation 16-16 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 229 Master mode BRT + 3 CLK_I2Cn TXSTART = 1 TXSTART = 0 STARTIF = 1 Slave mode Address matching the I2C_nOADR register BSY = 1 TR = 0/1 STARTIF = 1 Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 16-17 (Rev. 1.1)
Page 230 16.7 Control Registers I2C Ch.n Clock Control Register Register name Bit name Initial Reset Remarks I2C_nCLK 15–9 – 0x00 – – DBRUN 7–6 – – 5–4 CLKDIV[1:0] 3–2 – – 1–0 CLKSRC[1:0] Seiko Epson Corporation 16-18 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 231 Note: The I2C_nMOD register settings can be altered only when the I2C_nCTL.MODEN bit = 0. I2C Ch.n Baud-Rate Register Register name Bit name Initial Reset Remarks I2C_nBR 15–8 – 0x00 – – – – 6–0 BRT[6:0] 0x7f Bits 15–7 Reserved Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 16-19 (Rev. 1.1)
Page 232 STOP condition has been generated. This bit is automatically cleared when the bus free time (t defined in the I C Specifications) has elapsed after the STOP condition has been generated. Seiko Epson Corporation 16-20 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 233 Register name Bit name Initial Reset Remarks I2C_nRXD 15–8 – 0x00 – – 7–0 RXD[7:0] 0x00 Bits 15–8 Reserved Bits 7–0 RXD[7:0] The receive data buffer can be read through these bits. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 16-21 (Rev. 1.1)
Page 234 Bit 0 TBEIF These bits indicate the I2C interrupt cause occurrence status. 1 (R): Cause of interrupt occurred 0 (R): No cause of interrupt occurred 1 (W): Clear flag 0 (W): Ineffective Seiko Epson Corporation 16-22 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 235 I2C_nINTE.NACKIE bit: NACK reception interrupt I2C_nINTE.STOPIE bit: STOP condition interrupt I2C_nINTE.STARTIE bit: START condition interrupt I2C_nINTE.ERRIE bit: Error detection interrupt I2C_nINTE.RBFIE bit: Receive buffer full interrupt I2C_nINTE.TBEIE bit: Transmit buffer empty interrupt Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 16-23 (Rev. 1.1)
Page 236 (Ch.0–Ch.15) when a receive buffer full state has occurred. 1 (R/W): Enable DMA transfer request 0 (R/W): Disable DMA transfer request Each bit corresponds to a DMA controller channel. The high-order bits for the unimplemented chan- nels are ineffective. Seiko Epson Corporation 16-24 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 237 - The capture circuit captures counter values using external/software trigger signals and generates interrupts or DMA requests. (Can be used to measure external event periods/cycles.) Figure 17.1.1 shows the T16B configuration. Table 17.1.1 T16B Channel Configuration of S1C31W73 Item S1C31W73 Number of channels 2 channels (Ch.0 and Ch.1)
Page 238 If the port is shared with the T16B pin and other functions, the T16B input/output function must be assigned to the port before activating T16B. For more information, refer to the “I/O Ports” chapter. Seiko Epson Corporation 17-2 S1C31W73 TECHNICAL MANUAL (Rev. 0.15)
Page 239 Figure 17.3.4.1 Count Timing (During Count Up Operation) Note: When running the counter using the event counter clock, two dummy clocks must be input be- fore the first counting up/down can be performed. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 17-3 (Rev. 0.15)
Page 240 5. Set the following bits when using the interrupt: - Write 1 to the interrupt flags in the T16B_nINTF register. (Clear interrupt flags) - Set the interrupt enable bits in the T16B_nINTE register to 1. (Enable interrupts) Seiko Epson Corporation 17-4 S1C31W73 TECHNICAL MANUAL (Rev. 0.15)
Page 241 T16Bn, one of the operations shown below is required to read correctly by the CPU. - Read the counter value twice or more and check to see if the same value is read. - Stop the timer and then read the counter value. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 17-5 (Rev. 0.15)
Page 242 0x0000 and continues counting down from the new MAX value after a counter under- flow occurs. In one-shot down count mode, the counter returns to the MAX value if a counter underflow occurs and stops automatically at that point. Seiko Epson Corporation 17-6 S1C31W73 TECHNICAL MANUAL (Rev. 0.15)
Page 243 0x0000 and then starts counting up to the new MAX value. In one-shot up/down count mode, the counter stops automatically when it reaches 0x0000 during count down operation. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 17-7 (Rev. 0.15)
Page 244 When the counter reaches the MAX value in comparator mode, the T16B_nINTF.CNTMAXIF bit (counter MAX interrupt flag) is set to 1. When the counter reaches 0x0000, the T16B_nINTF.CNTZEROIF bit (counter zero interrupt flag) is set to 1. Seiko Epson Corporation 17-8 S1C31W73 TECHNICAL MANUAL (Rev. 0.15)
Page 245 Count cycle = — — — — — — — — [s] (Eq. 17.2) CLK_T16B CLK_T16B Where T16B_nCCRm register setting value (0 to 65,535) MAX: T16B_nMC register setting value (0 to 65,535) : Count clock frequency [Hz] CLK_T16B Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 17-9 (Rev. 0.15)
Page 246 (T16B_nMC register) Compare period Compare buffer Counter value Time 0x0000 CNTMAXIF = 1 CNTMAXIF = 1 CNTMAXIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 Seiko Epson Corporation 17-10 S1C31W73 TECHNICAL MANUAL (Rev. 0.15)
Page 247 Count cycle MAX value (T16B_nMC register) Compare period Compare buffer Counter value Time 0x0000 CNTMAXIF = 1 CNTMAXIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 17-11 (Rev. 0.15)
Page 248 Compare buffer value Compare period Time 0x0000 CNTZEROIF = 1 CNTZEROIF = 1 CNTZEROIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 Seiko Epson Corporation 17-12 S1C31W73 TECHNICAL MANUAL (Rev. 0.15)
Page 249 Time 0x0000 CNTMAXIF = 1 CNTZEROIF = 1 CNTMAXIF = 1 CNTZEROIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 17-13 (Rev. 0.15)
Page 250 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 (Note that the T16B_nINTF.CMPCAPmIF/CNTMAXIF/CNTZEROIF bit clearing operations via software are omitted from the figure.) Figure 17.4.3.2 Compare Buffer Operations Seiko Epson Corporation 17-14 S1C31W73 TECHNICAL MANUAL (Rev. 0.15)
Page 251 If the captured data stored in the T16B_nCCRm register is overwritten by the next trigger when the T16B_ nINTF.CMPCAPmIF bit is still set, an overwrite error occurs (the T16B_nINTF.CAPOWmIF bit is set). Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 17-15 (Rev. 0.15)
Page 252 Capture trigger signal T16B_nCCRm.CC[15:0] Capturing operation (2) Asynchronous capture mode (When T16B_nCCCTLm.CAPTRG[1:0] bits = 0x3) Count clock T16B_nTC.TC[15:0] Capture trigger signal T16B_nCCRm.CC[15:0] Capturing operation Figure 17.4.3.4 Synchronous Capture Mode/Asynchronous Capture Mode Seiko Epson Corporation 17-16 S1C31W73 TECHNICAL MANUAL (Rev. 0.15)
Page 253 Furthermore, when the T16B_nCCCTLm.TOUTMT bit is set to 1, the TOUT circuit uses the MATCH signal output from another system in the circuit pair (0 and 1, 2 and 3, 4 and 5). This makes it possible to change the signal twice within a counter cycle. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 17-17 (Rev. 0.15)
Page 254 Software control mode (0x0) Set mode (0x1) Toggle/reset mode (0x2) Set/reset mode (0x3) Toggle mode(0x4) Reset mode (0x5) Toggle/set mode (0x6) Reset/set mode (0x7) ∗ ( ) indicates the T16B_nCCCTLm.TOUTMD[2:0] bit-setting value. Seiko Epson Corporation 17-18 S1C31W73 TECHNICAL MANUAL (Rev. 0.15)
Page 255 Set/reset mode (0x3) Toggle mode(0x4) Reset mode (0x5) Toggle/set mode (0x6) Reset/set mode (0x7) ∗ ( ) indicates the T16B_nCCCTLm.TOUTMD[2:0] bit-setting value. Figure 17.4.4.2 TOUT Output Waveform (T16B_nCCCTLm.TOUTMT bit = 0) Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 17-19 (Rev. 0.15)
Page 256 Set/reset mode (0x3) TOUTn0 TOUTn1 Toggle mode(0x4) TOUTn0 TOUTn1 Reset mode (0x5) TOUTn0 TOUTn1 Toggle/set mode (0x6) TOUTn0 TOUTn1 Reset/set mode (0x7) TOUTn0 TOUTn1 ∗ ( ) indicates the T16B_nCCCTLm.TOUTMD[2:0] bit-setting value. Seiko Epson Corporation 17-20 S1C31W73 TECHNICAL MANUAL (Rev. 0.15)
Page 257 Set/reset mode (0x3) TOUTn0 TOUTn1 Toggle mode(0x4) TOUTn0 TOUTn1 Reset mode (0x5) TOUTn0 TOUTn1 Toggle/set mode (0x6) TOUTn0 TOUTn1 Reset/set mode (0x7) TOUTn0 TOUTn1 ∗ ( ) indicates the T16B_nCCCTLm.TOUTMD[2:0] bit-setting value. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 17-21 (Rev. 0.15)
Page 258 Toggle/set mode (0x6) TOUTn0 TOUTn1 Reset/set mode (0x7) TOUTn0 TOUTn1 ∗ ( ) indicates the T16B_nCCCTLm.TOUTMD[2:0] bit-setting value. Figure 17.4.4.3 TOUT Output Waveform (T16B_nCCCTL0.TOUTMT bit = 1, T16B_nCCCTL1.TOUTMT bit = 0) Seiko Epson Corporation 17-22 S1C31W73 TECHNICAL MANUAL (Rev. 0.15)
Page 259 Bit 8 DBRUN This bit sets whether the T16B Ch.n operating clock is supplied during debugging or not. 1 (R/W): Clock supplied during debugging 0 (R/W): No clock supplied during debugging Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 17-23 (Rev. 0.15)
Page 260 T16B_nCTL.ONEST bit setting (see Table 17.7.2). Bit 3 ONEST This bit selects the counter repeat/one-shot mode. The count mode is configured with this selection and the T16B_nCTL.CNTMD[1:0] bit settings (see Table 17.7.2). Seiko Epson Corporation 17-24 S1C31W73 TECHNICAL MANUAL (Rev. 0.15)
Page 261 T16B_nCTL.MODEN bit to 1 until the T16B_nCS.BSY bit is set to 0 from 1. • Do not set the T16B_nMC.MC[15:0] bits to 0x0000. T16B Ch.n Timer Counter Data Register Register name Bit name Initial Reset Remarks T16B_nTC 15–0 TC[15:0] 0x0000 – Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 17-25 (Rev. 0.15)
Page 262 This bit indicates the currently set count direction. 1 (R): Count up 0 (R): Count down Bit 0 This bit indicates the counter operating status. 1 (R): Running 0 (R): Idle Seiko Epson Corporation 17-26 S1C31W73 TECHNICAL MANUAL (Rev. 0.15)
Page 263 Note: The configuration of the T16B_nINTF.CAPOWmIF and T16B_nINTF.CMPCAPmIF bits depends on the model. The bits corresponding to the comparator/capture circuits that do not exist are read-only bits and are always fixed at 0. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 17-27 (Rev. 0.15)
Page 264 The bits corresponding to the comparator/capture circuits that do not exist are read-only bits and are always fixed at 0. • To prevent generating unnecessary interrupts, the corresponding interrupt flag should be cleared before enabling interrupts. Seiko Epson Corporation 17-28 S1C31W73 TECHNICAL MANUAL (Rev. 0.15)
Page 265 These bits select the trigger edge(s) of the trigger signal at which the counter value is captured in the T16B_nCCRm register in capture mode (see Table 17.7.4). The T16B_nCCCTLm.CAPTRG[1:0] bits are control bits for capture mode and are ineffective in comparator mode. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 17-29 (Rev. 0.15)
Page 266 T h e s i g n a l b e c o m e s i n a c t i v e b y t h e M AT C H m o r MATCHm+1 signal. TOUTnm+1 The signal becomes inactive by the MATCHm+1 or MATCHm signal. Seiko Epson Corporation 17-30 S1C31W73 TECHNICAL MANUAL (Rev. 0.15)
Page 267 In capture mode, this register is configured as the capture register and the counter value captured by the capture trigger signal is loaded. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 17-31 (Rev. 0.15)
Page 268 (Ch.0–Ch.15) when the counter value reaches the compare data or is captured. 1 (R/W): Enable DMA transfer request 0 (R/W): Disable DMA transfer request Each bit corresponds to a DMA controller channel. The high-order bits for the unimplemented chan- nels are ineffective. Seiko Epson Corporation 17-32 S1C31W73 TECHNICAL MANUAL (Rev. 0.15)
Page 269 Sound register MOSEL[1:0] Sound generation STIM[3:0] circuit BZOUT SINV Output control circuit SSTP #BZOUT Interrupt control circuit EMIE EMIF EDIE EDIF DMA request controller control circuit EMDMAENx Figure 18.1.1 SNDA Configuration Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 18-1 (Rev. 1.1)
Page 270 Piezoelectric buzzer #BZOUT S1C31 SNDA Figure 18.2.2.1 Connection between SNDA and Piezoelectric Buzzer (Direct Drive) Piezoelectric buzzer BZOUT S1C31 SNDA Figure 18.2.2.2 Connection between SNDA and Piezoelectric Buzzer (Single Pin Drive) Seiko Epson Corporation 18-2 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 271 Normal buzzer mode generates a buzzer signal with the software specified frequency and duty ratio, and outputs the generated signal to outside the IC. The buzzer output duration can also be controlled via software. An output start/stop procedure and the SNDA operations are shown below. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 18-3 (Rev. 1.1)
Page 272 Buzzer signal frequency [Hz] BZOUT DUTY: Buzzer signal duty ratio [%] However, the following settings are prohibited: • Settings as SNDADAT.SFRQ[7:0] bits ≤ SNDADAT.SLEN[5:0] bits • Settings as SNDADAT.SFRQ[7:0] bits = 0x00 Seiko Epson Corporation 18-4 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 273 – 71.9 35.9 0x15 – – – – 68.8 34.4 0x14 – – – – 65.6 32.8 0x13 – – – – 62.5 31.3 0x12 – – – – 59.4 29.7 Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 18-5 (Rev. 1.1)
Page 274 At the same time, the SNDAINTF.EDIF bit (sound output completion interrupt flag) is set to 1 and the SNDAINTF.SBSY bit is cleared to 0. Figure 18.4.3.1 shows a buzzer output timing chart in one-shot buzzer mode. Seiko Epson Corporation 18-6 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 275 At the same time, the SNDAINTF.EDIF bit (sound output completion interrupt flag) is set to 1 and the SNDAINTF.SBSY bit is cleared to 0. Figure 18.4.4.1 shows a melody mode operation timing chart. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 18-7 (Rev. 1.1)
Page 276 Dotted quarter rest 0x07 Quarter note Quarter rest 0x05 Dotted eighth note Dotted eighth rest 0x03 Eighth note Eighth rest 0x01 Sixteenth note Sixteenth rest 0x00 Thirty-second note Thirty-second rest Other Setting prohibited Seiko Epson Corporation 18-8 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 277 1 is register written to the SNDACTL.SSTP bit Sound output SNDAINTF.EDIF When a sound output has completed Writing 1 or writing to completion the SNDADAT register Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 18-9 (Rev. 1.1)
Page 278 Bit 7 Reserved Bits 6–4 CLKDIV[2:0] These bits select the division ratio of the SNDA operating clock. Bits 3–2 Reserved Bits 1–0 CLKSRC[1:0] These bits select the clock source of SNDA. Seiko Epson Corporation 18-10 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 279 This bit selects an output pin drive mode. 1 (R/W): Normal drive mode 0 (R/W): Direct drive mode For more information, refer to “Output Pin Drive Mode.” Bits 1–0 MOSEL[1:0] These bits select a sound output mode. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 18-11 (Rev. 1.1)
Page 280 0 (R/W): Note When a rest is selected, the BZOUT pin goes low and the #BZOUT pin goes high during the output duration. This bit is ignored in normal buzzer mode/one-shot buzzer mode. Seiko Epson Corporation 18-12 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 281 0x00 – – 7–2 – 0x00 – EMIE EDIE Bits 15–2 Reserved Bit 1 EMIE Bit 0 EDIE These bits enable SNDA interrupts. 1 (R/W): Enable interrupts 0 (R/W): Disable interrupts Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 18-13 (Rev. 1.1)
Page 282 (Ch.0–Ch.15) when a sound buffer empty state has occurred. 1 (R/W): Enable DMA transfer request 0 (R/W): Disable DMA transfer request Each bit corresponds to a DMA controller channel. The high-order bits for the unimplemented chan- nels are ineffective. Seiko Epson Corporation 18-14 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 283 • Automatic data setting function for continuous data transmission. • Output signal inverting function supporting various formats. • EL lamp drive waveform can be generated for an application example. Figure 19.1.1 shows the REMC3 configuration. Table 19.1.1 REMC3 Channel Configuration of S1C31W73 Item S1C31W73 Number of channels...
Page 284 1. Write 1 to the REMC3DBCTL.REMCRST bit. (Reset REMC3) 2. Configure the REMC3CLK.CLKSRC[1:0] and REMC3CLK.CLKDIV[3:0] bits. (Configure operating clock) 3. Assign the REMC3 output function to the port. (Refer to the “I/O Ports” chapter.) Seiko Epson Corporation 19-2 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 285 The REMC3 outputs the logical AND between the carrier signal output from the carrier generator and the data sig- nal output from the data signal generator. Figure 19.4.3.1 shows an example of the output waveform. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 19-3 (Rev. 1.1)
Page 286 The data signal is generated by comparing the values of the 16-bit counter for data signal generation (REMC3DBCNT.DBCNT[15:0] bits) that runs with CLK_REMC3 and the setting values of the REMC3A- PLEN.APLEN[15:0] and REMC3DBLEN.DBLEN[15:0] bits. Figure 19.4.3.3 shows an example of the data signal generated. Seiko Epson Corporation 19-4 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 287 (REMC3DBCTL.TRMD bit = 1), the counter stops automatically when the counter value is matched with the REMC3DBLEN.DBLEN[15:0] bit-setting value. 19.4.4 Continuous Data Transmission and Compare Buffers Figure 19.4.4.1 shows an operation example of continuous data transmission with the compare buffer enabled. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 19-5 (Rev. 1.1)
Page 288 The REMC3 provides interrupt enable bits corresponding to each interrupt flag. An interrupt request is sent to the CPU only when the interrupt flag, of which interrupt has been enabled by the interrupt enable bit, is set. For more information on interrupt control, refer to the “Interrupt” chapter. Seiko Epson Corporation 19-6 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 289 This bit sets whether the REMC3 operating clock is supplied during debugging or not. 1 (R/W): Clock supplied during debugging 0 (R/W): No clock supplied during debugging Bits 7–4 CLKDIV[3:0] These bits select the division ratio of the REMC3 operating clock. Bits 3–2 Reserved Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 19-7 (Rev. 1.1)
Page 290 This bit starts/stops counting by the internal counters (16-bit counter for data signal generation and 8-bit counter for carrier generation). 1 (W): Start counting 0 (W): Stop counting 1 (R): Counting 0 (R): Idle Seiko Epson Corporation 19-8 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 291 0x0000 H0/S0 Cleared by writing 1 to the REMC3DBCTL.REMCRST bit. Bits 15–0 DBCNT[15:0] The current value of the 16-bit counter for data signal generation can be read out through these bits. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 19-9 (Rev. 1.1)
Page 292 Transfer to the REMC3APLEN buffer has not completed. 0 (R): Transfer to the REMC3APLEN buffer has completed. While this bit is set to 1, writing to the REMC3APLEN.APLEN[15:0] bits is ineffective. Seiko Epson Corporation 19-10 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 293 REMC3CARR.CRPER[7:0] bit-setting value. (See Figure 19.4.3.2.) REMC3 Carrier Modulation Control Register Register name Bit name Initial Reset Remarks REMC3CCTL 15–9 – 0x00 – – OUTINVEN 7–1 – 0x00 – CARREN Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 19-11 (Rev. 1.1)
Page 294 This bit enables carrier modulation. 1 (R/W): Enable carrier modulation 0 (R/W): Disable carrier modulation (output data signal only) Note: When carrier modulation is disabled, the REMC3DBCTL.REMOINV bit should be set to 0. Seiko Epson Corporation 19-12 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 295 • Can convert multiple analog input signals sequentially. • Can generate conversion completion and overwrite error interrupts. • Can issue a DMA transfer request when a conversion has completed. Figure 20.1.1 shows the ADC12A configuration. Table 20.1.1 ADC12A Configuration of S1C31W73 Item S1C31W73 Number of channels 1 channel (Ch.0)
Page 296 : acquisition time). Figure 20.3.2.1 shows an equivalent circuit of the analog input portion. ADINnm ADIN ADIN Source impedance : Analog input resistance ADIN : Analog input capacitance ADIN Figure 20.3.2.1 Equivalent Circuit of Analog Input Portion Seiko Epson Corporation 20-2 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 297 Writing 1 to the ADC12A_nCTL.ADST bit enables the ADC12A to accept trigger inputs. After that, A/D con- version is started when an underflow occurs in the 16-bit timer Ch.k. Software trigger Writing 1 to the ADC12A_nCTL.ADST bit starts A/D conversion. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 20-3 (Rev. 1.1)
Page 298 3. Read the A/D conversion result of the analog input m (ADC12A_nADD.ADD[15:0] bits). 4. Repeat Steps 2 and 3 until terminating A/D conversion. 5. Write 0 to the ADC12A_nCTL.ADST bit. The ADC12A stops operating after the A/D conversion currently being executed has completed. Seiko Epson Corporation 20-4 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 299 The transfer source/destination and control data must be set for the DMA controller and the relevant DMA channel must be enabled to start a DMA transfer in advance. For more information on DMA, refer to the “DMA Controller” chapter. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 20-5 (Rev. 1.1)
Page 300 After a DMA transfer has completed, disable the DMA transfer to prevent unintended DMA transfer requests from being issued. For more information on the DMA control, refer to the “DMA Controller” chapter. Seiko Epson Corporation 20-6 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 301 Note: The data written to the ADC12A_nCTL.ADST bit must be retained for one or more CLK_T16_ k clock cycles when 1 is written or two or more CLK_T16_k clock cycles when 0 is written. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 20-7 (Rev. 1.1)
Page 302 Right justified (ADC12A_nTRG.STMD bit = 0) 0 (MSB) 12-bit conversion result (LSB) Figure 20.7.1 Conversion Data Alignment Bit 6 CNVMD This bit sets the A/D conversion mode. 1 (R/W): Continuous conversion mode 0 (R/W): One-time conversion mode Seiko Epson Corporation 20-8 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 303 A/D conversion. • Be aware that ADC circuit current I flows if the ADC12_nCFG.VRANGE[1:0] bits are set to a value other than 0x0 when the ADC12_nCTL.BSYSTAT bit = 1. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 20-9 (Rev. 1.1)
Page 304 0 (R/W): Disable interrupts The following shows the correspondence between the bit and interrupt: ADC12A_nINTE.OVIE bit: A/D conversion result overwrite error interrupt ADC12A_nINTE.ADmCIE bit: Analog input signal m A/D conversion completion interrupt Seiko Epson Corporation 20-10 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 305 ADC12A Ch.n Result Register Register name Bit name Initial Reset Remarks ADC12A_nADD 15–0 ADD[15:0] 0x0000 – Bits 15–0 ADD[15:0] The A/D conversion results are set to these bits. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 20-11 (Rev. 1.1)
Page 306 A/D converter. • Can supply the reference voltage generated in this circuit to external devices if this IC has the VREFA exclusive pin. Figure 21.1.1 shows the TSRVR configuration. Table 21.1.1 TSRVR Configuration of S1C31W73 Item S1C31W73 Number of channels 1 channel (Ch.0)
Page 307 ADD: A/D conversion result at temperature T or T (decimal) : A/D converter reference voltage [V] REFA For details of the internal A/D converter, refer to the “12-bit A/D Converter” chapter. Seiko Epson Corporation 21-2 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 308 TSRVR_nVCTL.VREFAMD[1:0] VREFA bits are set to 0x2 or 0x3. • When the TSRVR_nVCTL.VREFAMD[1:0] bits are not set to 0x0, do not apply an external voltage to the VREFAm pin. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 21-3 (Rev. 1.1)
Page 309 • Includes a power supply for 1/4 or 1/5 bias driving (allows external voltages to be applied). • Provides the frame signal monitoring output pin. • Can generate interrupts every frame. Figure 22.1.1 shows the LCD32C configuration. Table 22.1.1 LCD32C Configuration of S1C31W73 Item S1C31W73 Number of segments supported Max.
Page 310 Note: When the panel is connected, the LCD32CCTL.LCDDIS bit must be set to 1 to bias the panel even if display is turned off. COMm LCD Panel COM0 SEGn SEG0 S1C31 LCD32C Figure 22.2.2.1 Connections between LCD32C and an LCD Panel Seiko Epson Corporation 22-2 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 311 39.4 52.5 78.8 157.5 0x18 20.5 23.4 27.3 32.8 41.0 54.6 81.9 163.8 0x17 21.3 24.4 28.4 34.1 42.7 56.9 85.3 170.7 0x16 22.3 25.4 29.7 35.6 44.5 59.4 89.0 178.1 Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 22-3 (Rev. 1.1)
Page 312 85.3 93.1 102.4 113.8 0x02 85.3 91.0 97.5 105.0 113.8 124.1 136.5 151.7 0x01 128.0 136.5 146.3 157.5 170.7 186.2 204.8 227.6 0x00 256.0 273.1 292.6 315.1 341.3 372.4 409.6 455.1 Seiko Epson Corporation 22-4 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 313 12.2 12.6 13.1 13.7 0x0a 11.6 12.0 12.4 12.8 13.3 13.8 14.3 14.9 0x09 12.8 13.2 13.7 14.1 14.6 15.2 15.8 16.4 0x08 14.2 14.7 15.2 15.7 16.3 16.9 17.5 18.2 Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 22-5 (Rev. 1.1)
Page 314 LCD32CPWR.EXVCSEL bit to 1 and set both the LCD32CPWR.VCEN and LCD32CPWR.BSTEN bits to 0 to turn both the LCD voltage regulator and LCD voltage booster off. Figure 22.4.2.1 shows an external connection example for external voltage application mode. Seiko Epson Corporation 22-6 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 315 Set the booster clock frequency used in the LCD voltage booster using the LCD32CTIM2.BSTC[1:0] bits. Set it to the frequency that provides the best V –V output stability after being evaluated using the actual circuit board. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 22-7 (Rev. 1.1)
Page 316 All off (static drive) All on Normal display Display off When “Display off” is selected, the drive voltage supply stops and the LCD driver pin outputs are all set to V level. Seiko Epson Corporation 22-8 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 317 0x08 COM0–COM8 0x07 COM0–COM7 0x06 COM0–COM6 0x05 COM0–COM5 0x04 COM0–COM4 0x03 COM0–COM3 0x02 COM0–COM2 0x01 COM0–COM1 0x00 Static COM0 Unused common pins output an OFF waveform that turns the segments off. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 22-9 (Rev. 1.1)
Page 318 *1 The COM pins to be used depend on the drive duty selection. For more information, refer to “Drive Duty Switching.” 22.5.5 Drive Waveforms Figures 22.5.5.1 to 22.5.5.8 show drive waveform examples. Seiko Epson Corporation 22-10 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 319 COM0 COM0 COM1 COM2 COM3 COM4 COM5 COM1 COM6 COM24 COM25 COM26 COM28 COM2 COM29 COM30 COM31 SEGx COM30 COM31 SEGx Figure 22.5.5.1 1/32 Duty Drive Waveform (1/5 bias) Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 22-11 (Rev. 1.1)
Page 320 COM29 COM30 COM31 (= V SEGx COM30 (= V COM31 (= V (= V (= V SEGx (= V (= V (= V Figure 22.5.5.2 1/32 Duty Drive Waveform (1/4 bias) Seiko Epson Corporation 22-12 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 321 COM0 COM0 COM1 COM2 COM3 COM4 COM5 COM1 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM2 COM13 COM14 COM15 SEGx COM14 COM15 SEGx Figure 22.5.5.3 1/16 Duty Drive Waveform (1/5 bias) Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 22-13 (Rev. 1.1)
Page 322 COM13 COM14 COM15 (= V SEGx COM14 (= V COM15 (= V (= V (= V SEGx (= V (= V (= V Figure 22.5.5.4 1/16 Duty Drive Waveform (1/4 bias) Seiko Epson Corporation 22-14 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 323 22 LCD DRIVER (LCD32C) 1 frame LFRO display status COM0 COM0 COM1 COM2 COM3 COM4 COM5 COM1 COM6 COM7 SEGx COM2 COM6 COM7 SEGx Figure 22.5.5.5 1/8 Duty Drive Waveform (1/5 bias) Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 22-15 (Rev. 1.1)
Page 324 SEGx (= V COM2 (= V COM6 (= V COM7 (= V (= V (= V SEGx (= V (= V (= V Figure 22.5.5.6 1/8 Duty Drive Waveform (1/4 bias) Seiko Epson Corporation 22-16 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 325 Note that using the n-line inverse AC drive function increases current consumption. Table 22.5.7.1 Selecting Number of Inverse Lines LCD32CTIM2.NLINE[4:0] bits Number of inverse lines 0x1f 31 lines 0x1e 30 lines 0x01 1 line 0x00 Normal drive Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 22-17 (Rev. 1.1)
Page 326 When the LCD32CDSP.COMREV bit is set to 1, memory bits are assigned to common pins in ascending order. When the LCD32CDSP.COMREV bit is set to 0, memory bits are assigned to common pins in descending order. Seiko Epson Corporation 22-18 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 327 COM7 COM25 COM6 COM26 COM5 COM27 COM4 COM28 COM3 COM29 COM2 COM30 COM1 COM31 COM0 LCD32CDSP. · · · SEGREV bit = 1 LCD32CDSP. · · · SEGREV bit = 0 Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 22-19 (Rev. 1.1)
Page 328 COM3 COM29 COM2 COM30 COM1 COM31 COM0 LCD32CDSP. · · · SEGREV bit = 1 LCD32CDSP. · · · SEGREV bit = 0 Figure 22.6.3.1 Display Data RAM Map (1/32 duty) Seiko Epson Corporation 22-20 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 329 COM5 COM19 COM4 COM20 COM3 COM21 COM2 COM22 COM1 COM23 COM0 Unused area (general-purpose RAM) LCD32CDSP. · · · SEGREV bit = 1 LCD32CDSP. · · · SEGREV bit = 0 Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 22-21 (Rev. 1.1)
Page 330 COM1 COM23 COM0 Unused area (general-purpose RAM) LCD32CDSP. · · · SEGREV bit = 1 LCD32CDSP. · · · SEGREV bit = 0 Figure 22.6.3.2 Display Data RAM Map (1/24 duty) Seiko Epson Corporation 22-22 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 331 COM5 COM11 COM4 COM12 COM3 COM13 COM2 COM14 COM1 COM15 COM0 Unused area (general-purpose RAM) LCD32CDSP. · · · SEGREV bit = 1 LCD32CDSP. · · · SEGREV bit = 0 Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 22-23 (Rev. 1.1)
Page 332 COM1 COM15 COM0 Unused area (general-purpose RAM) LCD32CDSP. · · · SEGREV bit = 1 LCD32CDSP. · · · SEGREV bit = 0 Figure 22.6.3.3 Display Data RAM Map (1/16 duty) Seiko Epson Corporation 22-24 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 333 = 1 bit = 0 Display area 0 COM0 COM0 Unused area (general-purpose RAM) LCD32CDSP. · · · SEGREV bit = 1 LCD32CDSP. · · · SEGREV bit = 0 Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 22-25 (Rev. 1.1)
Page 334 Display area 1 COM0 COM0 Unused area (general-purpose RAM) LCD32CDSP. · · · SEGREV bit = 1 LCD32CDSP. · · · SEGREV bit = 0 Figure 22.6.3.4 Display Data RAM Map (static drive) Seiko Epson Corporation 22-26 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 335 Bit 7 Reserved Bits 6–4 CLKDIV[2:0] These bits select the division ratio of the LCD32C operating clock. Bits 3–2 Reserved Bits 1–0 CLKSRC[1:0] These bits select the clock source of the LCD32C. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 22-27 (Rev. 1.1)
Page 336 12–8 FRMCNT[4:0] 0x01 7–5 – – 4–0 LDUTY[4:0] 0x1f Bits 15–13 Reserved Bits 12–8 FRMCNT[4:0] These bits set the frame frequency. For more information, refer to “Frame Frequency.” Bits 7–5 Reserved Seiko Epson Corporation 22-28 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 337 “n-Segment-Line Inverse AC Drive.” LCD32C Power Control Register Register name Bit name Initial Reset Remarks LCD32CPWR EXVCSEL – 14–12 – – 11–8 LC[3:0] 7–6 – – DBLEN BSTEN BIASSEL HVLD – – VCEN Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 22-29 (Rev. 1.1)
Page 338 VCEN This bit turns the LCD voltage regulator on and off. 1 (R/W): LCD voltage regulator on 0 (R/W): LCD voltage regulator off For more information, refer to “LCD Power Supply.” Seiko Epson Corporation 22-30 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 339 LCD32C COM Pin Control Registers 0 and 1 Register name Bit name Initial Reset Remarks LCD32CCOMC0 COM15DEN – COM14DEN COM13DEN COM12DEN COM11DEN COM10DEN COM9DEN COM8DEN COM7DEN COM6DEN COM5DEN COM4DEN COM3DEN COM2DEN COM1DEN COM0DEN Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 22-31 (Rev. 1.1)
Page 340 LCD32CINTE 15–8 – 0x00 – – 7–1 – 0x00 – FRMIE Bits 15–1 Reserved Bit 0 FRMIE This bit enables the frame interrupt. 1 (R/W): Enable interrupt 0 (R/W): Disable interrupt Seiko Epson Corporation 22-32 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 341 • Can generate reference oscillation completion, sensor (A and B) oscillation completion, measurement counter overflow error, and time base counter overflow error interrupts. Figure 23.1.1 shows the RFC configuration. Table 23.1.1 RFC Channel Configuration of S1C31W73 Item S1C31W73 Number of channels 1 channel (Ch.0)
Page 342 Figure 23.2.2.1 Connection Example in Resistive Sensor DC Oscillation Mode SENBn SEN1 SENAn REFn RFINn : Reference resistor : Resistive sensor (AC bias) SEN1 S1C31 RFC : Reference capacitor Figure 23.2.2.2 Connection Example in Resistive Sensor AC Oscillation Mode Seiko Epson Corporation 23-2 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 343 (Clear interrupt flags) - Set the interrupt enable bits in the RFC_nINTE register to 1. (Enable interrupts) 3. Assign the RFC input/output function to the ports. (Refer to the “I/O Ports” chapter.) Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 23-3 (Rev. 1.1)
Page 344 To obtain the difference between the reference oscillation and sensor oscillation clock count values from the measurement counter simply, appropriate initial values must be set to the measurement counter before starting reference oscillation. Seiko Epson Corporation 23-4 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 345 The measurement counter overflow sets the RFC_nINTF.EREFIF bit to 1 indicating that the reference os- cillation has been terminated normally. If the RFC_nINTE.EREFIE bit = 1, a reference oscillation comple- tion interrupt request occurs at this point. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 23-5 (Rev. 1.1)
Page 346 Performing reference oscillation and sensor oscillation with the same resistor and capacitor results n ≈ m. The difference between n and m is a conversion error. Table 23.4.4.1 lists the error factors. (n: measurement counter initial value, m: measurement counter value at the end of sensor oscillation) Seiko Epson Corporation 23-6 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 347 The RFC provides interrupt enable bits corresponding to each interrupt flag. An interrupt request is sent to the CPU only when the interrupt flag, of which interrupt has been enabled by the interrupt enable bit, is set. For more infor- mation on interrupt control, refer to the “Interrupt” chapter. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 23-7 (Rev. 1.1)
Page 348 This bit sets the RFCLKOn pin to output the divided-by-two oscillation clock. 1 (R/W): Divided-by-two clock output 0 (R/W): Oscillation clock output For more information, refer to “CR Oscillation Frequency Monitoring Function.” Seiko Epson Corporation 23-8 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 349 This bit controls CR oscillation for sensor A. This bit also indicates the CR oscillation status. 1 (W): Start oscillation 0 (W): Stop oscillation 1 (R): Being oscillated 0 (R): Stopped Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 23-9 (Rev. 1.1)
Page 350 Note: The time base counter must be set from the low-order value (RFC_nTCL.TC[15:0] bits) first when data is set using a 16-bit access instruction. The counter may not be set to the correct value if the high-order value (RFC_nTCH.TC[23:16] bits) is written first. Seiko Epson Corporation 23-10 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 351 RFC_nINTE.OVTCIE bit: Time base counter overflow error interrupt RFC_nINTE.OVMCIE bit: Measurement counter overflow error interrupt RFC_nINTE.ESENBIE bit: Sensor B oscillation completion interrupt RFC_nINTE.ESENAIE bit: Sensor A oscillation completion interrupt RFC_nINTE.EREFIE bit: Reference oscillation completion interrupt Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 23-11 (Rev. 1.1)
Page 352 • Incorporates total 256-byte FIFO for endpoints (64 bytes for each endpoint). • Includes a PLL for generating the 48 MHz USB clock Figure 24.1.1 shows the USB controller configuration. Table 24.1.1 USB Controller Configuration of S1C31W73 Item S1C31W73 Endpoints...
Page 353 (5 V) or Pxx = tolerant fail-safe port *2 When V < V (5 V) and Pxx ≠ tolerant fail-safe port Figure 24.2.2.1 Connections between USB controller and an External USB Device Seiko Epson Corporation 24-2 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 354 Characteristics”) until the output voltage can be used after they start operating. For the regulator control timings, refer to Section 24.5.1, “List of Input/Output Pins.” Note: Configure the V regulator voltage mode to mode0 when operating the USB controller. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 24-3 (Rev. 1.1)
Page 355 3. Activate the OSC3 oscillator circuit after setting the oscillation stabilization waiting time and interrupt (refer to the “Clock Generator” section in the “Power Supply, Reset, and Clocks” chapter). This operation is not required when the OSC3 oscillator circuit is stably operating already. Seiko Epson Corporation 24-4 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 356 24.5.2 Settings when V is Disconnected Use the Pxx port for detecting V disconnection (Detach) and perform the processing shown below when an in- terrupt has occurred at the falling edge of the input. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 24-5 (Rev. 1.1)
Page 357 1. The host issues a SETUP token addressed to EP0 of this node. 2. Next, the host sends an 8-byte data packet. 3. The USB controller writes this data to the USBEP0SETUP0 to 7 registers. Seiko Epson Corporation 24-6 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 358 5a. The USB controller does not update the FIFO. 6a. The USB controller does not set the USBEPnINTF.OUTACKIF bit. 7a. The USB controller does not set the USBEPmINTF.OUTSHACKIF and USBEPmCTL.FNAK bits. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 24-7 (Rev. 1.1)
Page 359 Control transfer on EP0 consists of a setup stage, a data stage, and a status stage that are controlled as a combina- tion of a number of discrete transactions. A control transfer sequence for an OUT data stage is shown below. Seiko Epson Corporation 24-8 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 360 If the FIFO has an available space, the USB controller automatically receives data. For more information, refer to “OUT transfer” in Section 24.5.6, “Data Flow Control.” Furthermore, monitor the USBEP0INTF.INNAKIF bit (an interrupt can be used) and transit to the status stage if it is set. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 24-9 (Rev. 1.1)
Page 361 Bulk and interrupt transfers at a general-purpose endpoint EPm, can be controlled either as a data flow (refer to Section 24.5.6, “Data Flow Control”) or as a series of discrete transactions (refer to Section 24.5.3, “Transaction Control”). Seiko Epson Corporation 24-10 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 362 Figure 24.5.6.2 shows a data flow in IN transfer. In this example, the FIFO area assigned to this endpoint is as- sumed to be twice as large as the maximum packet size. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 24-11 (Rev. 1.1)
Page 363 Detach processing, therefore, this function should be enabled after Attach has detected and disabled after Detach is detected. Check each interrupt flag (USBSIEINTF.RESETIF bit and USBSIEINTF.SUSPENDIF bit) to confirm what has been actually detected. Seiko Epson Corporation 24-12 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 364 USBSIEINTF.RESETIF bit or the USBSIEINTF.SUSPENDIF bit is set and a Reset detection or Suspend detection interrupt is generated. If the state is determined to be Suspend, the USB controller enters IN_SUSPEND state. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 24-13 (Rev. 1.1)
Page 365 J state Last activity USB_DP/USB_DM pins J state Internal USB clock Fully meet USB 2.0 required frequency * The SNOOZE signal should be controlled using the USBMISCCTL.USBSNZ bit. Figure 24.5.8.1 Suspend Timing Seiko Epson Corporation 24-14 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 366 The description above assumes that the oscillator circuit is operating (the 48-MHz clock is supplied to the USB controller, and the CPU is not in SLEEP mode). If the CPU is in SLEEP mode and the oscillator is deactivated, an oscillation stabilization waiting time is required before resuming. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 24-15 (Rev. 1.1)
Page 367 "00" (Normal operation mode) USBSTAT.LINESTAT[1:0] J state USB_DP/USB_DM pins FS Idle (J state) Internal USB clock Fully meet USB 2.0 required frequency Clock stabilization waiting time Figure 24.5.8.3 Device Attach Timing Seiko Epson Corporation 24-16 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 368 Therefore, unless the descriptor area has been changed, there is no need to re-set the infor- mation recorded within the area since it will never be cleared otherwise. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 24-17 (Rev. 1.1)
Page 369 The transfer source/destination and control data must be set for the DMA controller and the relevant DMA channel must be enabled to start a DMA transfer in advance. For more information on DMA, refer to the “DMA Controller” chapter. Seiko Epson Corporation 24-18 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 370 Notes: • Be sure to avoid accessing to the USB controller for five 48-MHz clock cycles from the SNOOZE signal being asserted/negated. • Be sure to avoid accessing to the FIFO while the 48 MHz clock is stopped after the SNOOZE signal is asserted. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 24-19 (Rev. 1.1)
Page 371 * These interrupt flags are provided to easily determine the cause of the interrupt generated; they indicate that an interrupt flag in an interrupt group of which interrupt has been enabled is set. Seiko Epson Corporation 24-20 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 372 Note: Do not perform 32-bit access to read and write from/to the USB registers as it may cause mal- function. USB Control Register Register name Bit name Initial Reset Remarks USBCTL BUSDETDIS H0/S0 – AUTONEGOEN H0/S0 NONJDETEN H0/S0 JDETEN H0/S0 WAKEUP H0/S0 2–1 – – USBEN H0/S0 Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 24-21 (Rev. 1.1)
Page 373 Since this bit is cleared to 0 after an initial reset, all USB functions are stopped. The operation as a USB device will be enabled by setting this bit to 1 after the configuration of this USB controller has completed. Seiko Epson Corporation 24-22 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 374 Note: This bit is fixed at 1, as this IC supports FS mode only. Bits 5–2 Reserved Bits 1–0 LINESTAT[1:0] These bits indicate the USB bus status (signal status at the USB_DP and USB_DM pins). Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 24-23 (Rev. 1.1)
Page 375 This bit clears the EPc FIFO. 1 (R/W): Clear EPc FIFO 0 (R/W): Ineffective Writing 1 to this bit clears the EPc FIFO only. After that, this bit automatically reverts to 0. Seiko Epson Corporation 24-24 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 376 – USBEP0SETUP7 7–0 WLEN[15:8] 0x00 – – Eight-byte data received at EP0 SETUP stage are stored from the USBEP0SETUP0 register sequentially. The con- tents stored in each register are listed below. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 24-25 (Rev. 1.1)
Page 377 USB EP0 Maximum Packet Size Register Register name Bit name Initial Reset Remarks USBEP0SIZE – – – 6–3 MAXSIZE[3:0] H0/S0 2–0 – Bit 7 Reserved Bits 6–3 MAXSIZE[3:0] These bits set the EP0 maximum packet size. Seiko Epson Corporation 24-26 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 378 This bit clears the toggle sequence bit in the IN transaction of EP0, to 0. 1 (W): Clear toggle sequence bit 0 (W): Ineffective 0 (R): Always 0 when being read Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 24-27 (Rev. 1.1)
Page 379 This bit clears the toggle sequence bit in the OUT transaction of EP0, to 0. 1 (W): Clear toggle sequence bit 0 (W): Ineffective 0 (R): Always 0 when being read Seiko Epson Corporation 24-28 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 380 USBEPmCTL.SPKTEN bit is set to 1, that data may be included in transmission. Therefore, do not write data into the FIFO until the packet transmission completes and this bit is cleared. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 24-29 (Rev. 1.1)
Page 381 Initial Reset Remarks USBEPmCFG H0/S0 – TGLMOD H0/S0 EPEN H0/S0 – – 3–0 EPNUM[3:0] H0/S0 Bit 7 This bit sets the transfer direction of EPm. 1 (R/W): IN 0 (R/W): OUT Seiko Epson Corporation 24-30 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 382 EPBRD Bit 0 EPARD These bits specify the endpoint from which FIFO data is read. 1 (R/W): Enable reading data from EPm FIFO 0 (R/W): Disable reading data from EPm FIFO Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 24-31 (Rev. 1.1)
Page 383 1 (R/W): Enable USBWRFIFOSEL register 0 (R/W): Disable USBWRFIFOSEL register When this bit is set to 1, the CPU can write data to the FIFO of the endpoint selected by the USB- WRFIFOSEL register. Seiko Epson Corporation 24-32 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 384 USBEPmINTF register. 5–2 – – – EP0IF H0/S0 Cleared by writing 1 to the interrupt flag in the USBEP0INTF register. EP0SETIF H0/S0 Cleared by writing 1. Bits 5–2 Reserved Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 24-33 (Rev. 1.1)
Page 385 Bit 0 ATADDRIF These bits indicate the SIE interrupt cause occurrence status. 1 (R): Cause of interrupt occurred 0 (R): No cause of interrupt occurred 1 (W): Clear flag 0 (W): Ineffective Seiko Epson Corporation 24-34 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 386 Register name Bit name Initial Reset Remarks USBEP0INTF 7–6 – – – INACKIF H0/S0 Cleared by writing 1. OUTACKIF H0/S0 INNAKIF H0/S0 OUTNAKIF H0/S0 INERRIF H0/S0 OUTERRIF H0/S0 Bits 7–6 Reserved Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 24-35 (Rev. 1.1)
Page 387 Bit 0 OUTERRIF These bits indicate the EPm interrupt cause occurrence status. 1 (R): Cause of interrupt occurred 0 (R): No cause of interrupt occurred 1 (W): Clear flag 0 (W): Ineffective Seiko Epson Corporation 24-36 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 388 USB SIE Interrupt Enable Register Register name Bit name Initial Reset Remarks USBSIEINTE (reserved) H0/S0 – NONJIE H0/S0 RESETIE H0/S0 SUSPENDIE H0/S0 SOFIE H0/S0 H0/S0 – – ATADDRIE H0/S0 Bit 7 Reserved Bit 1 Reserved Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 24-37 (Rev. 1.1)
Page 389 GPEPIE bit must be set to 1 in addition to this register. USB EP0 Interrupt Enable Register Register name Bit name Initial Reset Remarks USBEP0INTE 7–6 – – – INACKIE H0/S0 OUTACKIE H0/S0 INNAKIE H0/S0 OUTNAKIE H0/S0 INERRIE H0/S0 OUTERRIE H0/S0 Seiko Epson Corporation 24-38 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 390 EPm ACK reception interrupt USBEPmINTE.OUTACKIE bit: EPm ACK transmission interrupt USBEPmINTE.INNAKIE bit: EPm NAK reception interrupt USBEPmINTE.OUTNAKIE bit: EPm NAK transmission interrupt USBEPmINTE.INERRIE bit: EPm STALL reception interrupt USBEPmINTE.OUTERRIE bit: EPm STALL transmission interrupt Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 24-39 (Rev. 1.1)
Page 391 This bit sets the number of bus access cycles for accessing a USB register. Table 24.8.5 Number of Bus Access Cycles for Accessing USB register USBMISCCTL.USBWAIT bit Number of bus access cycles System clock frequency 33 MHz (max.) 8 MHz (max.) Seiko Epson Corporation 24-40 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 392 1 (R/W): Regulator On 0 (R/W): Regulator Off Bit 0 REG33VEN This bit turns the 3.3 V regulator for the PHY on or off. 1 (R/W): Regulator On 0 (R/W): Regulator Off Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 24-41 (Rev. 1.1)
Page 393 (USBREMDATCNT.REMDAT[6:0] bits ≠ 0). 1 (R/W): Enable DMA transfer request 0 (R/W): Disable DMA transfer request Each bit corresponds to a DMA controller channel. The high-order bits for the unimplemented chan- nels are ineffective. Seiko Epson Corporation 24-42 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 394 *5 R are not required when using the debug pins as general-purpose I/O ports. DBG1–2 *6 The component values should be determined after evaluating operations using an actual mounting board. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 25-1 (Rev. 1.1)
Page 395 *1 OSC1 oscillator: CLGOSC1.OSC1SELCR bit = 0, CLGOSC1.INV1N[1:0] bits = 0x0, CLGOSC1.CGI1[2:0] bits = 0x0, CLGOSC1. OSDEN bit = 0, C = 0 pF, Crystal resonator = C-002RX (manufactured by Seiko Epson Corporation, R = 50 kW (Max.), = 7 pF) *2 OSC1 oscillator: CLGOSC1.OSC1SELCR bit = 1...
Page 396 IOSC = OFF, OSC1 = 32.768 kHz, OSC3 = OFF, Typ. value IOSC = OFF, OSC1 = 32.768 kHz, OSC3 = 16 MHz (ceramic oscillator), Ta = 25°C, CLGOSC3.OSC3INV[1:0] bits = 0x2, Typ. value Ta [°C] Ta [°C] Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 25-3 (Rev. 1.1)
Page 397 = 0 V, Ta = -40 to 105°C Item Symbol Condition Min. Typ. Max. Unit Reset hold time ｍs RSTR *1 Time until the internal reset signal is negated after the reset request is canceled. Seiko Epson Corporation 25-4 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 398 = 2.0 to 5.5 V, PWGACTL.REGSEL bit = 1, Typ. value = 2.0 to 5.5 V, PWGACTL.REGSEL bit = 0, Typ. value CLGIOSC.IOSCFQ[2:0] bits = 0x7 CLGIOSC.IOSCFQ[2:0] bits = 0x1 Ta [°C] Ta [°C] Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 25-5 (Rev. 1.1)
Page 399 CLGOSC1.OSC1SELCR bit = 1, 27.84 36.16 Ta = -40 to 105°C *1 CLGOSC1.CGI1[2:0] bits = 0x0, Crystal resonator = C-002RX (manufactured by Seiko Epson Corporation, R = 50 kW (Max.), C = 7 pF) OSC1 internal oscillation frequency-temperature characteristic = 1.8 to 5.5 V, Typ. value Ta [°C]...
Page 400 Low level output current = 0.1 × V – – Leakage current – µA LEAK Input pull-up resistance Input pull-down resistance Pin capacitance – – High level Low level Input voltage [V] Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 25-7 (Rev. 1.1)
Page 401 SVD4_0CTL.SVDC[4:0] bits = 0x1b 1,101 1,211 SVD4_0CTL.SVDC[4:0] bits = 0x1c 1,012 1,125 1,237 1,149 SVD4_0CTL.SVDC[4:0] bits = 0x1d 1,034 1,264 1,173 SVD4_0CTL.SVDC[4:0] bits = 0x1e 1,055 1,290 SVD4_0CTL.SVDC[4:0] bits = 0x1f 1,077 1,197 1,316 Seiko Epson Corporation 25-8 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 402 SVD4_0CTL.SVDC[4:0] bits = 0x1d 4.61 4.99 SVD4_0CTL.SVDC[4:0] bits = 0x1e 4.70 5.10 SVD4_0CTL.SVDC[4:0] bits = 0x1f 4.80 5.20 – – SVD circuit enable response time µs SVDEN SVD circuit response time – – µs Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 25-9 (Rev. 1.1)
Page 403 = 1.8 to 5.5 V, V = 0 V, Ta = -40 to 105°C Item Symbol Condition Min. Typ. Max. Unit Transfer baud rate Normal mode – 460,800 BRT1 IrDA mode – 115,200 BRT2 Seiko Epson Corporation 25-10 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 404 SDI1 hold time – mode0 – – – mode1 – – SDO1 output delay time = 15 pF – mode0 – – – mode1 – – *1 C = Pin load Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 25-11 (Rev. 1.1)
Page 405 (CPOL, CPHA) = (1, 0) or (0, 1) SPICLKn (CPOL, CPHA) = (1, 1) or (0, 0) SDIn SDOn Slave mode #SPISSn SPICLKn (CPOL, CPHA) = (0, 1) SPICLKn (CPOL, CPHA) = (1, 0) SDIn Hi-Z SDOn Seiko Epson Corporation 25-12 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 406 QSDIOn[3:0] output stop time = 15 pF 3.0 to 5.5 V mode0 – – 1.8 to 3.0 V mode0 – – 1.8 to 3.6 V mode1 – – *1 C = Pin load Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 25-13 (Rev. 1.1)
Page 407 5.22 5.50 5.77 LCD32CPWR.LC[3:0] bits = 0xc 5.30 5.58 5.86 LCD32CPWR.LC[3:0] bits = 0xd 5.37 5.66 5.94 LCD32CPWR.LC[3:0] bits = 0xe 5.45 5.73 6.02 LCD32CPWR.LC[3:0] bits = 0xf 5.52 5.81 6.10 Seiko Epson Corporation 25-14 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 408 *1 Other LCD driver settings: LCD32CPWR.LC[3:0] bits = 0xf, CLK_LCD32C = 32 kHz, LCD32CTIM1.FRMCNT[4:0] bits = 0x01 (frame frequency = 64 Hz) *2 The value is added to the current consumption in HALT/RUN mode. Current consumption increases according to the display contents and panel load. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 25-15 (Rev. 1.1)
Page 409 Ta = 25°C, Typ. value, LCD32CPWR.LC[3:0] bits = 0xf, when a load is connected to the V pin only when a load is connected to the V pin only [µA] [µA] Seiko Epson Corporation 25-16 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 410 = 100 kW, Ta = 25°C, Typ. value 1,000 1,000 5.5 V 5.5 V 3.6 V 3.6 V 1.8 V 1.8 V ∆f /∆IC ∆f /∆IC RFCLK RFCLK 1,000 10,000 1,000 10,000 100,000 [kΩ] [pF] Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 25-17 (Rev. 1.1)
Page 411 *1 The Max. value is the value when the A/D conversion clock frequency f = 2,000 kHz. CLK_ADC12A *2 Integral nonlinearity is measured at the end point line. *3 The error will be increased according to the potential difference between V and VREFAn. Seiko Epson Corporation 25-18 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 412 – – µs TEMP 0x1–0x3 TSRVR_nVCTL.VREFAMD[1:0] Invalid Valid VREFAn VREFA TSRVR_nTCTL.TEMPEN Invalid Valid Temperature sensor output TEMP Temperature sensor output voltage-temperature characteristic = 2.2 to 5.5 V, Typ. value Ta [°C] Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 25-19 (Rev. 1.1)
Page 413 USB circuit current Ta = 25°C – *1 Current flowing through the V pin in HID device class (1 transfer per ms) USB circuit current-V voltage characteristic Ta = 25°C, Typ. value Seiko Epson Corporation 25-20 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 414 *3: When 1/5 bias is selected *4: When the LCD circuit power supply voltage booster is used (V ≤ 2.5 V) *5: When OSC1 crystal oscillator is selected ( ): Do not mount components if unnecessary. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 26-1 (Rev. 1.1)
Page 415 Symbol Name Recommended components X'tal1 32 kHz crystal resonator C-002RX (R = 50 kW (Max.), C = 7 pF) manufactured by Seiko Epson Corporation OSC1 gate capacitor Trimmer capacitor or ceramic capacitor OSC1 drain capacitor Ceramic capacitor X’tal3 Crystal resonator...
Page 416 27 PACKAGE 27 Package QFP21-216PIN (P-LQFP216-2424-0.40) INDEX 0.13 /0.27 0.09 /0.2 0° /10° /0.7 Figure 27.1 QFP21-216PIN Package Dimensions Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL 27-1 (Rev. 1.1)
Page 417 – – – 0046 (CLG OSC1 Control OSDRB R/WP Register) OSDEN R/WP OSC1BUP R/WP OSC1SELCR R/WP 10–8 CGI1[2:0] R/WP 7–6 INV1B[1:0] R/WP 5–4 INV1N[1:0] R/WP 3–2 – – 1–0 OSC1WT[1:0] R/WP Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL AP-A-1 (Rev. 1.1)
Page 418 – – 0062 (SRC #RESET Port – – Control Register) 6–4 (reserved) R/WP Do not write 1. – – – (reserved) R/WP Do not write 1. PORT_PLUP_EN R/WP – PORT_RESET_EN R/WP Seiko Epson Corporation AP-A-2 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 419 11–8 RTCHLA[3:0] – – 6–4 RTCMIHA[2:0] 3–0 RTCMILA[3:0] 0x4000 RTCASWCTL 15–12 BCD10[3:0] – 00c6 (RTCA Stopwatch 11–8 BCD100[3:0] Control Register) 7–5 – – SWRST Read as 0. 3–1 – – – SWRUN Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL AP-A-3 (Rev. 1.1)
Page 420 T1MINIF T1SECIF T1_2SECIF T1_4SECIF T1_8SECIF T1_32SECIF 0x4000 RTCAINTE RTCTRMIE – 00d2 (RTCA Interrupt En- SW1IE able Register) SW10IE SW100IE 11–9 – – ALARMIE T1DAYIE T1HURIE T1MINIE T1SECIE T1_2SECIE T1_4SECIE T1_8SECIE T1_32SECIE Seiko Epson Corporation AP-A-4 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 421 Flash Controller (FLASHC) Address Register name Bit name Initial Reset Remarks 0x4000 FLASHCWAIT 15–8 – 0x00 – – 01b0 (FLASHC Flash Read 7–2 – 0x00 – Cycle Register) 1–0 RDWAIT[1:0] R/WP Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL AP-A-5 (Rev. 1.1)
Page 422 (P1 Port Mode Select 7–0 P1SEL[7:0] 0x00 Register) 0x4000 PPORTP1FNCSEL 15–14 P17MUX[1:0] – 021e (P1 Port Function 13–12 P16MUX[1:0] Select Register) 11–10 P15MUX[1:0] 9–8 P14MUX[1:0] 7–6 P13MUX[1:0] 5–4 P12MUX[1:0] 3–2 P11MUX[1:0] 1–0 P10MUX[1:0] Seiko Epson Corporation AP-A-6 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 423 11–10 P35MUX[1:0] 9–8 P34MUX[1:0] 7–6 P33MUX[1:0] 5–4 P32MUX[1:0] 3–2 P31MUX[1:0] 1–0 P30MUX[1:0] 0x4000 PPORTP4DAT 15–13 – – – 0240 (P4 Port Data 12–8 P4OUT[4:0] 0x00 Register) 7–5 – – 4–0 P4IN[4:0] 0x00 Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL AP-A-7 (Rev. 1.1)
Page 424 (P5 Port Function 13–12 P56MUX[1:0] Select Register) 11–10 P55MUX[1:0] 9–8 P54MUX[1:0] 7–6 P53MUX[1:0] 5–4 P52MUX[1:0] 3–2 P51MUX[1:0] 1–0 P50MUX[1:0] 0x4000 PPORTP6DAT 15–8 P6OUT[7:0] 0x00 – 0260 (P6 Port Data 7–0 P6IN[7:0] 0x00 Register) Seiko Epson Corporation AP-A-8 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 425 3–2 P71MUX[1:0] 1–0 P70MUX[1:0] 0x4000 PPORTP8DAT 15–8 P8OUT[7:0] 0x00 – 0280 (P8 Port Data 7–0 P8IN[7:0] 0x00 Register) 0x4000 PPORTP8IOEN 15–8 P8IEN[7:0] 0x00 – 0282 (P8 Port Enable 7–0 P8OEN[7:0] 0x00 Register) Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL AP-A-9 (Rev. 1.1)
Page 426 7–4 CLKDIV[3:0] R/WP 3–2 KRSTCFG[1:0] R/WP 1–0 CLKSRC[1:0] R/WP 0x4000 PPORTINTFGRP 15–9 – 0x00 – – 02e2 (P Port Interrupt Flag P8INT Group Register) P7INT P6INT P5INT P4INT P3INT P2INT P1INT P0INT Seiko Epson Corporation AP-A-10 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 427 10–8 P17PERISEL[2:0] Setting Register) 7–5 P16PPFNC[2:0] 4–3 P16PERICH[1:0] 2–0 P16PERISEL[2:0] 0x4000 UPMUXP2MUX0 15–13 P21PPFNC[2:0] – 0310 (P20–21 Universal 12–11 P21PERICH[1:0] Port Multiplexer 10–8 P21PERISEL[2:0] Setting Register) 7–5 P20PPFNC[2:0] 4–3 P20PERICH[1:0] 2–0 P20PERISEL[2:0] Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL AP-A-11 (Rev. 1.1)
Page 428 Register name Bit name Initial Reset Remarks 0x4000 UART3_0CLK 15–9 – 0x00 – – 0380 (UART3 Ch.0 Clock DBRUN Control Register) 7–6 – – 5–4 CLKDIV[1:0] 3–2 – – 1–0 CLKSRC[1:0] Seiko Epson Corporation AP-A-12 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 429 3–0 TBEDMAEN[3:0] Empty DMA Request Enable Register) 0x4000 UART3_0 15–8 – 0x00 – – 0392 RB1FDMAEN 7–4 – – (UART3 Ch.0 Receive Buffer One Byte Full 3–0 RB1FDMAEN[3:0] DMA Request Enable Register) Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL AP-A-13 (Rev. 1.1)
Page 430 7–2 – 0x00 – Register) SFTRST MODEN 0x4000 SPIA_0TXD 15–0 TXD[15:0] 0x0000 – 03b4 (SPIA Ch.0 Transmit Data Register) 0x4000 SPIA_0RXD 15–0 RXD[15:0] 0x0000 – 03b6 (SPIA Ch.0 Receive Data Register) Seiko Epson Corporation AP-A-14 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 431 I2C_0TXD 15–8 – 0x00 – – 03cc (I2C Ch.0 Transmit 7–0 TXD[7:0] 0x00 Data Register) 0x4000 I2C_0RXD 15–8 – 0x00 – – 03ce (I2C Ch.0 Receive 7–0 RXD[7:0] 0x00 Data Register) Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL AP-A-15 (Rev. 1.1)
Page 432 5–4 CNTMD[1:0] ONEST PRESET MODEN 0x4000 T16B_0MC 15–0 MC[15:0] 0xffff – 0404 (T16B Ch.0 Max Counter Data Register) 0x4000 T16B_0TC 15–0 TC[15:0] 0x0000 – 0406 (T16B Ch.0 Timer Counter Data Register) Seiko Epson Corporation AP-A-16 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 433 – 0412 (T16B Ch.0 Compare/ Capture 0 Data Register) 0x4000 T16B_0CC0DMAEN 15–8 – 0x00 – – 0414 (T16B Ch.0 Compare/ 7–4 – – Capture 0 DMA Request Enable 3–0 CC0DMAEN[3:0] Register) Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL AP-A-17 (Rev. 1.1)
Page 434 – 042a (T16B Ch.0 Compare/ Capture 3 Data Register) 0x4000 T16B_0CC3DMAEN 15–8 – 0x00 – – 042c (T16B Ch.0 Compare/ 7–4 – – Capture 3 DMA Request Enable 3–0 CC3DMAEN[3:0] Register) Seiko Epson Corporation AP-A-18 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 435 Enable Register) CMPCAP3IE CAPOW2IE CMPCAP2IE CAPOW1IE CMPCAP1IE CAPOW0IE CMPCAP0IE CNTMAXIE CNTZEROIE 0x4000 T16B_1MZDMAEN 15–8 – 0x00 – – 044e (T16B Ch.1 Counter 7–4 – – Max/Zero DMA Request Enable 3–0 MZDMAEN[3:0] Register) Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL AP-A-19 (Rev. 1.1)
Page 436 – 0462 (T16B Ch.1 Compare/ Capture 2 Data Register) 0x4000 T16B_1CC2DMAEN 15–8 – 0x00 – – 0464 (T16B Ch.1 Compare/ 7–4 – – Capture 2 DMA Request Enable 3–0 CC2DMAEN[3:0] Register) Seiko Epson Corporation AP-A-20 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 437 04a0 (T16 Ch.4 Clock DBRUN Control Register) 7–4 CLKDIV[3:0] 3–2 – – 1–0 CLKSRC[1:0] 0x4000 T16_4MOD 15–8 – 0x00 – – 04a2 (T16 Ch.4 Mode 7–1 – 0x00 – Register) TRMD Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL AP-A-21 (Rev. 1.1)
Page 438 Register name Bit name Initial Reset Remarks 0x4000 UART3_1CLK 15–9 – 0x00 – – 0600 (UART3 Ch.1 Clock DBRUN Control Register) 7–6 – – 5–4 CLKDIV[1:0] 3–2 – – 1–0 CLKSRC[1:0] Seiko Epson Corporation AP-A-22 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 439 3–0 TBEDMAEN[3:0] Empty DMA Request Enable Register) 0x4000 UART3_1 15–8 – 0x00 – – 0612 RB1FDMAEN 7–4 – – (UART3 Ch.1 Receive Buffer One Byte Full 3–0 RB1FDMAEN[3:0] DMA Request Enable Register) Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL AP-A-23 (Rev. 1.1)
Page 440 7–2 – 0x00 – Register) SFTRST MODEN 0x4000 SPIA_1TXD 15–0 TXD[15:0] 0x0000 – 0674 (SPIA Ch.1 Transmit Data Register) 0x4000 SPIA_1RXD 15–0 RXD[15:0] 0x0000 – 0676 (SPIA Ch.1 Receive Data Register) Seiko Epson Corporation AP-A-24 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 441 (T16 Ch.2 Interrupt 7–1 – 0x00 – Flag Register) UFIF Cleared by writing 1. 0x4000 T16_2INTE 15–8 – 0x00 – – 068c (T16 Ch.2 Interrupt 7–1 – 0x00 – Enable Register) UFIE Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL AP-A-25 (Rev. 1.1)
Page 442 (QSPI Ch.0 Memory 7–4 – – Mapped Access Con- 3–0 TCSH[3:0] figuration Register 1) 0x4000 QSPI_0RMADRH 15–4 RMADR[31:20] 0x000 – 06a4 (QSPI Ch.0 Remap- ping Start Address High Register) 3-0 – – Seiko Epson Corporation AP-A-26 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 443 I2C_1TXD 15–8 – 0x00 – – 06cc (I2C Ch.1 Transmit 7–0 TXD[7:0] 0x00 Data Register) 0x4000 I2C_1RXD 15–8 – 0x00 – – 06ce (I2C Ch.1 Receive 7–0 RXD[7:0] 0x00 Data Register) Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL AP-A-27 (Rev. 1.1)
Page 444 SNDACTL 15–9 – 0x00 – – 0704 (SNDA Control SSTP Register) 7–1 – 0x00 – MODEN 0x4000 SNDADAT MDTI – 0706 (SNDA Data MDRS Register) 13–8 SLEN[5:0] 0x00 7–0 SFRQ[7:0] 0xff Seiko Epson Corporation AP-A-28 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 445 Cleared by writing 1 to this bit or the REMC3DBCTL. APIF H0/S0 REMCRST bit. 0x4000 REMC3INTE 15–8 – 0x00 – – 072c (REMC3 Interrupt 7–2 – 0x00 – Enable Register) DBIE APIE Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL AP-A-29 (Rev. 1.1)
Page 446 10–8 STAAIN[2:0] Select Register) STMD CNVMD 5–4 CNVTRG[1:0] – – 2–0 SMPCLK[2:0] 0x4000 ADC12A_0CFG 15–8 – 0x00 – – 07a6 (ADC12A Ch.0 Con- 7–2 – 0x00 – figuration Register) 1–0 VRANGE[1:0] Seiko Epson Corporation AP-A-30 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 447 0x4000 ADC12A_0DMAEN7 15–8 – 0x00 – – 07ba (ADC12A Ch.0 DMA 7–4 – – Request Enable 3–0 ADCDMAEN[3:0] Register 7) 0x4000 ADC12A_0ADD 15–0 ADD[15:0] 0x0000 – 07bc (ADC12A Ch.0 Result Register) Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL AP-A-31 (Rev. 1.1)
Page 448 7–6 – – DBLEN BSTEN BIASSEL HVLD – – VCEN 0x4000 LCD32CDSP 15–8 – 0x00 – – 080a (LCD32C Display – – Control Register) SEGREV COMREV DSPREV – – DSPAR 1–0 DSPC[1:0] Seiko Epson Corporation AP-A-32 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 449 7–6 – – 5–4 CLKDIV[1:0] 3–2 – – 1–0 CLKSRC[1:0] 0x4000 RFC_0CTL 15–9 – 0x00 – – 0842 (RFC Ch.0 Control RFCLKMD Register) CONEN EVTEN 5–4 (reserved) – 3–1 – – MODEN Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL AP-A-33 (Rev. 1.1)
Page 450 EPMFSTALLSET H0/S0 Control Register) EPNFIFOCLR H0/S0 4–1 – – EP0FIFOCLR H0/S0 0x2040 USBGPEPFIFOCLR 7–3 – 0x00 – – 0009 (USB General-Purpose EPCFIFOCLR H0/S0 Endpoint FIFO Clear EPBFIFOCLR H0/S0 Register) EPAFIFOCLR H0/S0 Seiko Epson Corporation AP-A-34 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 451 FSTALL H0/S0 0x2040 USBEP0OCTL AUTOFNAK H0/S0 – 001d USB EP0 OUT 6–5 – H0/S0 Transaction Control TGLSTAT H0/S0 Register) TGLSET H0/S0 Read as 0. TGLCLR H0/S0 FNAK H0/S0 – FSTALL H0/S0 Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL AP-A-35 (Rev. 1.1)
Page 452 0040 (USB Read FIFO EPCRD H0/S0 Select Register) EPBRD H0/S0 EPARD H0/S0 0x2040 USBWRFIFOSEL 7–3 – 0x00 – – 0041 (USB Write FIFO EPCWR H0/S0 Select Register) EPBWR H0/S0 EPAWR H0/S0 Seiko Epson Corporation AP-A-36 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 453 OUTERRIF H0/S0 0x2040 USBEPAINTF – – – 0054 (USB EPa Interrupt OUTSHACKIF H0/S0 Cleared by writing 1. Flag Register) INACKIF H0/S0 OUTACKIF H0/S0 INNAKIF H0/S0 OUTNAKIF H0/S0 INERRIF H0/S0 OUTERRIF H0/S0 Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL AP-A-37 (Rev. 1.1)
Page 454 OUTNAKIE H0/S0 INERRIE H0/S0 OUTERRIE H0/S0 0x2040 USBEPBINTE – – – 0065 (USB EPb Interrupt OUTSHACKIE H0/S0 Enable Register) INACKIE H0/S0 OUTACKIE H0/S0 INNAKIE H0/S0 OUTNAKIE H0/S0 INERRIE H0/S0 OUTERRIE H0/S0 Seiko Epson Corporation AP-A-38 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 455 0x4000 DMACCPTR 31–7 CPTR[31:7] 0x000 – 1008 (DMAC Control Data 0000 Base Pointer Register) 6–0 CPTR[6:0] 0x00 0x4000 DMACACPTR 31–0 ACPTR[31:0] – – 100c (DMAC Alternate Control Data Base Pointer Register) Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL AP-A-39 (Rev. 1.1)
Page 456 Cleared by writing 1. 0x4000 DMACENDIF 31–24 – 0x00 – 2000 (DMAC Transfer 23–16 – 0x00 – Completion Interrupt 15–8 – 0x00 – Flag Register) 7–4 – – 3–0 ENDIF[3:0] Cleared by writing 1. Seiko Epson Corporation AP-A-40 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 457 – ERRIESET 0x4000 DMACERRIECLR 31–24 – 0x00 – – 2014 (DMAC Error Interrupt 23–16 – 0x00 – Enable Clear Register) 15–8 – 0x00 – 7–1 – 0x00 – ERRIECLR – – Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL AP-A-41 (Rev. 1.1)
Page 458 • Using a crystal resonator with lower C value decreases current consumption. However, these configurations may reduce the oscillation margin and increase the frequency error, therefore, be sure to perform matching evaluation using the actual printed circuit board. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL AP-B-1 (Rev. 1.1)
Page 459 • Turning the LCD circuit power supply voltage booster on (LCD32CPWR.DBLEN bit = 1) increases current consumption. The LCD circuit power supply voltage booster should be turned on only when V is lower than 2.5 V. Seiko Epson Corporation AP-B-2 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 460 Sudden power supply fluctuations due to noise will cause malfunctions. Consider the following issues. (1) Connections from the power supply to the V and V pins should be implemented via the shortest, thick- est patterns possible. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL AP-C-1 (Rev. 1.1)
Page 461 (2) Electromagnetically-induced noise from a solder iron when soldering In particular, during soldering, take care to ensure that the soldering iron GND (tip potential) has the same po- tential as the IC GND. Seiko Epson Corporation AP-C-2 S1C31W73 TECHNICAL MANUAL (Rev. 1.1)
Page 462 The resistance value should be determined by evaluating it on the mounting board. When connecting a power supply directly to the VREFA pin, insert a 100 W resistor in series. This resistance does not affect the A/D converter characteristics. Seiko Epson Corporation S1C31W73 TECHNICAL MANUAL AP-D-1 (Rev. 1.1)
Page 463 REVISION HISTORY Revision History Code No. Page Contents 414076300 New establishment 414076301 Whole Corrected the Cortex ® -M0+ register names. manual System control register → Cortex ® -M0+ System Control Register Cortex ® -M0+ Application Interrupt and Reset Control Register Vector table offset register →...
Page 464 REVISION HISTORY Code No. Page Contents 414076301 10-4 10.4.2 Real-Time Clock Counter Operations Corrective operation when a value out of the effective range is set Added a note. Note: Do not set the RTCMON.RTCMOL[3:0] bits to 0x0 if the RTCMON.RTCMOH bit = 0. 10-11 10.6 Control Registers RTCA Month/Day Register...
Page 465 REVISION HISTORY Code No. Page Contents 414076301 17-5 17.4.2 Counter Block Operations MAX counter data register Added a note. Note: When rewriting the MAX value, the new MAX value should be written after the counter has been reset to the previously set MAX value. 22-2 22.2.1 List of Output Pins Modified Table 22.2.1.1.
Page 466 Phone: +86-755-3299-0588 Fax: +86-755-3299-0560 Epson Europe Electronics GmbH Riesstrasse 15, 80992 Munich, Germany Epson Taiwan Technology & Trading Ltd. Phone: +49-89-14005-0 Fax: +49-89-14005-110 15F, No. 100, Songren Rd, Sinyi Dist, Taipei City 110, Taiwan Phone: +886-2-8786-6688 Epson Singapore Pte., Ltd.