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ADM1060
CONFIGURATION DOWNLOAD AT POWER- UP
The configuration of the ADM1060- the UV/OV thresh-
olds, glitch filter timeouts, PLB combinations, PDO pull-
ups etc, is dictated by the contents of the RAM. The
RAM is comprised of local latches which set the configu-
ration. These latches are double buffered and are actually
comprised of 2 identical latches (Latch A and Latch B).
An update of the double- buffered latch updates Latch A
first then Latch B. The advantage of this architecture is
explained below.
These latches are volatile memory and
lose their contents at power- down. Therefore, at power-
up the configuration in the RAM must be restored. This
is achieved by downoading the contents of the EEPROM
(non- volatile memory) to the local latches.
load occurs in a number of steps.
1. With no power applied to the device, the PDO's are all
high impedance.
2. Once 1V appears on any of the inputs connected to the
VDD Arbitrator (VH or VPn), the PDO's are all (weakly)
pulled to GND.
3. Once the supply rises above the Undervoltage Lockout
of the device (UVLO is 2.5V), the EEPROM starts to
download to the RAM.
4. The EEPROM downloads its contents to all Latch A's.
5. Once the contents of the EEPROM are completely
downloaded, the device controller outputs a control pulse
enabling all Latch A's to download to all Latch B's, thus
completing the configuration download.
communicate with the device prior to this download
completion will result in a NACK being issued from the
ADM1060.
UPDATING THE CONFIGURATION OF THE
ADM1060
Once powered up, with all of the configuration settings
loaded from EEPROM into the RAM registers, the user
may wish to alter the configuration of functions on the
ADM1060 (eg) change the UV or OV limit of an SFD,
change the fault output of an SFD, change the timeout of
the Watchdog Detector, change the rise time delay of one
of the PDO's etc.
The ADM1060 provides a number of options which allow
the user to update the configuration differently over the
SMBus interface.
All of these options are controlled in
the register UPDCFG.
1. Update the configuration in real time. The user writes
to RAM across the SMBus and the configuration is up-
dated immediately.
2. Update A Latches "offline" and then update all B
Latches at the same time. With this method, the configu-
ration of the ADM1060 will remain unchanged and con-
tinue to operate in the original setup until the instruction
is given to update the B Latches.
3. Change EEPROM register contents "offline" and then
download the revised EEPROM contents to the RAM
registers. Again, with this method, the configuration of the
ADM1060 will remain unchanged and continue to operate
PRELIMINARY TECHNICAL DATA
This down-
Any attempt to
The options are:-
PROGRAMMING ADM1060
in the original setup until the instruction is given to
change.
The instruction to download from the EEPROM in option
3 above is also a useful way to restore the original
EEPROM contents if revisions to the configuration are
unsatisfactory to the user and they wish the ADM1060 to
return to a known operating mode.
This type of operation is possible because of the topology
of the ADM1060. The Local (volatile) registers, or RAM,
are all double buffered latches. Setting bit 0 of the
UPDCFG register to 1 leaves the double buffered latches
open at all times.
write occurs across the SMBus only the first side of the
double buffered latch is written to. The user must then
write a 1 to bit 1 of the UPDCFG register. This gener-
ates a pulse to update all of the second latches at once.
Similarly with EEPROM writes.
A final bit in this register is used to enable EEPROM
page erasure. If this bit is set high, then the contents of an
EEPROM page can all be set to 0. If low, then the con-
tents of a page cannot be erased, even if the command
code for page erasure is programmed across the SMBus.
The bitmap for register UPDCFG is shown below.
flow chart for download at power up and subsequent con-
figuration updates is shown overleaf:-
–36–
If bit 0 is set to 0, then when RAM
A
REV. PrJ 11/02
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