Analog Devices ADM1060 Manual page 25

Communications system supervisory/sequencing circuit
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ADM1060 LOGIC
2
1
0
TABLE 31. BIT MAP FOR PnSFDIMKA/PnSFDIMKB REGISTERS (POWER- ON DEFAULT 00H)
Bit
7
6-0
6
5
4
3
2
1
0
TABLE 32. BIT MAP FOR PnGPIPOL REGISTERS (POWER- ON DEFAULT 00H)
Bit
7-4
3-0
7
Function A
6
5
4
3
Function B
2
1
0
REV. PrJ 11/02
PRELIMINARY TECHNICAL DATA
V H
V B 2
V B 1
Name
R/W
Description
Reserved N/A
Cannot be used
IGN7-IGN1
R / W
PLB1
Function A
03H
Function B
0BH
V P 4
V P 3
V P 2
V P 1
V H
V B 2
V B 1
Name
R/W
Description
APOL4-APOL1
R / W
BPOL4-BPOL1
R / W
PLB1
04H
GPI1
GPI2
GPI3
GPI4
GPI1
GPI2
GPI3
GPI4
V H
V H
V H
V B 2
V B 2
V B 2
V B 1
V B 1
V B 1
If high, mask the SFDn input before it is used in function A or B
PLB2
PLB3
PLB4
13H
23H
33H
1BH
2BH
3BH
V P 4
V P 4
V P 4
V P 3
V P 3
V P 3
V P 2
V P 2
V P 2
V P 1
V P 1
V P 1
V H
V H
V H
V B 2
V B 2
V B 2
V B 1
V B 1
V B 1
If high, invert the GPIn input before it is used in function A
If high, invert the GPIn input before it is used in function B
PLB2
PLB3
PLB4
14H
24H
34H
GPI1
GPI1
GPI1
GPI2
GPI2
GPI2
GPI3
GPI3
GPI3
GPI4
GPI4
GPI4
GPI1
GPI1
GPI1
GPI2
GPI2
GPI2
GPI3
GPI3
GPI3
GPI4
GPI4
GPI4
–25–
V H
V H
V H
V B 2
V B 2
V B 2
V B 1
V B 1
V B 1
PLB5
PLB6
PLB7
43H
53H
63H
4BH
5BH
6BH
V P 4
V P 4
V P 4
V P 3
V P 3
V P 3
V P 2
V P 2
V P 2
V P 1
V P 1
V P 1
V H
V H
V H
V B 2
V B 2
V B 2
V B 1
V B 1
V B 1
PLB5
PLB6
PLB7
44H
54H
64H
GPI1
GPI1
GPI1
GPI2
GPI2
GPI2
GPI3
GPI3
GPI3
GPI4
GPI4
GPI4
GPI1
GPI1
GPI1
GPI2
GPI2
GPI2
GPI3
GPI3
GPI3
GPI4
GPI4
GPI4
ADM1060
V H
V H
V B 2
V B 2
V B 1
V B 1
PLB8
PLB9
73H
83H
7BH
8BH
V P 4
V P 4
V P 3
V P 3
V P 2
V P 2
V P 1
V P 1
V H
V H
V B 2
V B 2
V B 1
V B 1
PLB8
PLB9
74H
84H
GPI1
GPI1
GPI2
GPI2
GPI3
GPI3
GPI4
GPI4
GPI1
GPI1
GPI2
GPI2
GPI3
GPI3
GPI4
GPI4

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