Analog Devices ADM1060 Manual page 18

ADM1060
(ie) Not Connected
PLB1
PLB2
INVERT 00H P1PLBPOLA.0
01H P1PLBIMKA.0
IGNORE
PLB3
INVERT 00H P1PLBPOLA.1
IGNORE 01H P1PLBIMKA.1
PLB4
INVERT 00H P1PLBPOLA.2
IGNORE 01H P1PLBIMKA.2
PLB5
00H P1PLBPOLA.3
INVERT
01H P1PLBIMKA.3
IGNORE
PLB6
INVERT 00H P1PLBPOLA.4
IGNORE 01H P1PLBIMKA.4
PLB7
INVERT 00H P1PLBPOLA.5
IGNORE 01H P1PLBIMKA.5
PLB8
INVERT 00H P1PLBPOLA.6
IGNORE 01H P1PLBIMKA.6
PLB9
INVERT 00H P1PLBPOLA.7
IGNORE 01H P1PLBIMKA.7
VB1
INVERT 02H P1SFDPOLA.0
IGNORE 03H P1SFDIMKA.0
VB2
02H P1SFDPOLA.1
INVERT
03H P1SFDIMKA.1
IGNORE
VH
02H P1SFDPOLA.2
INVERT
03H P1SFDIMKA.2
IGNORE
VP1
INVERT 02H P1SFDPOLA.3
IGNORE 03H P1SFDIMKA.3
VP2
INVERT 02H P1SFDPOLA.4
03H P1SFDIMKA.4
IGNORE
VP3
INVERT 02H P1SFDPOLA.5
IGNORE 03H P1SFDIMKA.5
VP4
INVERT 02H P1SFDPOLA.6
03H P1SFDIMKA.6
IGNORE
GPI1
INVERT 04H P1GPIPOL.4
05H P1GPIIMK.4
IGNORE
GPI2
INVERT 04H P1GPIPOL.5
IGNORE 05H P1GPIIMK.5
GPI3
INVERT 04H P1GPIPOL.6
05H P1GPIIMK.6
IGNORE
GPI4
INVERT 04H P1GPIPOL.7
IGNORE 05H P1GPIIMK.7
WDI_P
INVERT 06H P1WDICFG.7
IGNORE 06H P1WDICFG.6
WDI_L
INVERT 06H P1WDICFG.5
06H P1WDICFG.4
IGNORE
PRELIMINARY TECHNICAL DATA
Figure 5. Detailed Diagram for function A of PLB1
The diagram shown highlights all 21 inputs to a given
function and the register/ bits which need to be set in
order to condition the 21 inputs correctly. The diagram
only shows function A of Programmable Logic Block 1
(PLB1) but all functions are programmed in the same way.
If, as an example, the user wishes to assert PLBOUT
200ms after all of the supplies are in spec. (PLBOUT may
be used to drive the enable pin of an LDO) then the
supply fault detectors VBn, VH and VPn are required to
control the function. The function is programmed as
follows:-
• The IGNORE bit of all the other inputs (GPI's, PDB's
WDI) in the relevant P1xxxIMK registers is set to 1.
Thus, regardless of their status, the input to the function
AND gate for these inputs will be 1.
• Since the SFD's assert a 1 under a fault condition and a
0 when the supplies are in tolerance, the SFD outputs
need to be inverted before being applied to the function.
Thus the relevant bit in the P1SFDPOL register is set
(See Table Y).
• The function is enabled (bit 1 of register P1EN- Table
Z))
• A rise time of 200ms is programmed (register
P1PDBTIM- see register map overleaf for details)
ENABLE
FUNCTION A
07H P1EN.1
TO
FUNCTION B
–18–
ADM1060 LOGIC
RISE TIME
0CH P1PDBTIM.7-4
PDB
0CH P1PDBTIM.3-0
FALL TIME
07H P1EN.2
REV. PrJ 11/02
PLBOUT