Table of Contents
Advertisement
ADM1060
TABLE 36. LIST OF REGISTERS FOR PROGRAMMABLE DELAY BLOCK (PDB)
Hex
Table
Addr.
0 C
37
1 C
37
2 C
37
3 C
37
4 C
37
5 C
37
6 C
37
7 C
37
8 C
37
TABLE 37. PnPDBTIM REGISTERS 0Ch,1CH,2CH,3CH,4CH,5CH,6CH,7CH,8CH
Bit
Name
7-4
TR3-TR0
3-0
TF3-TF0
PRELIMINARY TECHNICAL DATA
Name
Default
Power On Value
P1PDBTIM
00h
P2PDBTIM
00h
P3PDBTIM
00h
P4PDBTIM
00h
P5PDBTIM
00h
P6PDBTIM
00h
P7PDBTIM
00h
P8PDBTIM
00h
P9PDBTIM
00h
R/W
W
W
Description
Delay for PDB1. Delay for rising edge and falling edge pro
grammed separately.
Delay for PDB2. Delay for rising edge and falling edge pro
grammed separately.
Delay for PDB3. Delay for rising edge and falling edge prog
rammed separately.
Delay for PDB4. Delay for rising edge and falling edge pro
grammed separately.
Delay for PDB5. Delay for rising edge and falling edge pro
grammed separately.
Delay for PDB6. Delay for rising edge and falling edge pro
grammed separately.
Delay for PDB7. Delay for rising edge and falling edge pro
grammed separately.
Delay for PDB8. Delay for rising edge and falling edge pro
grammed separately.
Delay for PDB9. Delay for rising edge and falling edge pro
grammed separately.
Description
Programmed Rise Time
Programmed Fall Time
TR3
TR2
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
TF3
TF2
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
–28–
ADM1060 LOGIC
TR1
TR0
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
TF1
TF0
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
REV. PrJ 11/02
Delay(ms)
0
1
2
5
10
20
40
60
80
100
150
200
250
300
400
500
Delay(ms)
0
1
2
5
10
20
40
60
80
100
150
200
250
300
400
500
Advertisement
Table of Contents
