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ADM1060
WATCHDOG FAULT DETECTOR
The ADM1060 has a Watchdog Fault Detector.
be used to monitor a processor clock to ensure normal
operation.
The detector monitors the WDI pin, expecting
there to be a low-to-high or high to low transition within a
preprogrammed period.
can be programmed from 200msec to a maximum of
12.8sec.
If no transition is detected, 2 signals are asserted. One is
a latched high signal, indicating a fault has occurred. The
other signal is a low- high- low pulse which can be used as
a RESET signal for a processor core. The width of this
pulse can be programmed (from 10 s to a maximum of
10ms). These two Watchdog signals can be selected as
inputs to each of the PLB's (see PLBA section). They
TABLE 18. LIST OF REGISTERS FOR WATCHDOG FAULT DETECTOR
Hex
Table
Address
9 C
19
TABLE 19. REGISTER 9CH WDCFG (POWER- ON DEFAULT 00H)
Bit
Name
7-5
Reserved
4-3
PULS1-PULS0
2-0
PER3-PER0
PRELIMINARY TECHNICAL DATA
The watchdog timeout period
Name
W D C F G
can also be inverted, if required (eg) if a high- low- high
This can
pulse was required by a processor to reset. Thus, a fault
on the watchdog can be used to generate a pulsed or
latched output on any or all of the 9 PDO's.
The latched signal can be cleared low by reading LATF1,
then LATF2 across the SMBus interface (see Fault Regis-
ters section). The RAM register list and the bit map for
the Watchdog Fault Detector are shown below.
Default
Description
Power On Value
00h
Program length Watchdog timeout and length of pulsed output
R/W
Description
R / W
Unused
R / W
Length of pulse outputted once the Watchdog Detector has timed out
PULS1
PULS0
0
0
0
1
1
0
1
1
R / W
Watchdog Timeout Period
PER2
PER1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
–14–
ADM1060 INPUTS
Pulse Length Selected ( s)
10
100
1000
10000
PER0
Watchdog Timeout selected (ms)
0
Disabled
1
200
0
400
1
800
0
1600
1
3200
0
6400
1
12800
REV. PrJ 11/02
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