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PROGRAMMING ADM1060
TABLE 52. LIST OF CONFIGURATION UPDATE REGISTERS
Hex
Table
Addr.
90
53
TABLE 53. BIT MAP FOR UPDCFG REGISTER 90H (POWER- ON DEFAULT 00H)
Bit
7-4
3
2
1
0
POWER- UP
(Vcc >2.5V)
E
E
P
R
O
M
L
D
EEPROM
REV. PrJ 11/02
PRELIMINARY TECHNICAL DATA
Name
Default
Power On Value
U P D C F G
00h
Name
R/W
Reserved
N/A
EE_ERASE
R / W
EEPROMLD
W
R A M L D
W
UPD
R / W
SMBus
DEVICE
CONTROLLER
D
A
T
A
LATCH A
Figure 8. Configuration Update Flow Diagram
Description
Configuration Update Control register for changing
configuration of the ADM1060 after power- up
Description
Cannot be used
If set high, then EEPROM page erasure can be programmed.
If set high, the ADM1060 will download the contents of its EEPROM to the RAM
registers. This bit self clears (returns to 0) after the download
If set high, the ADM1060 will download the buffered RAM register data into the
local latches. This bit self clears (returns to 0) after the download
If set high, the ADM1060 will update its configuration in real time as a word is
written to a local RAM register via the SMBus
R
U
A
P
M
D
L
D
–37–
ADM1060
FUNCTION
LATCH B
(eg) O V T hreshold
on VP1
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