Analog Devices ADM1060 Manual page 5

Communications system supervisory/sequencing circuit
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ADM1060–SPECIFICATIONS
(VH=4.5V to 14.4V, VPn = 3.0V to 6.0V
Parameter
PROGRAMMABLE DRIVER
OUTPUTS
High Voltage (Charge Pump) Mode
(PDO's 1 to 4)
Output Impedance, R
OUT
V
O H
I
OUTAVG
Standard (Digital Output) Mode
(PDO's 1 to 9)
V
O H
V
O L
I
SINK
R
Weak Pull-up
PULLUP-
I
SOURCE (VPn)
Tristate Output Leakage Current
DIGITAL INPUTS
(GPI 1-4,WDI,A0,A1)
Input High Voltage, V
Input Low Voltage, V
IL
Input High Current, I
Input Low Current, I
IL
Input Capacitance
Programmable Pulldown Current, I
SERIAL BUS DIGITAL INPUTS
(SDA,SCL)
Input High Voltage, V
Input Low Voltage, V
IL
Output Low Voltage, V
PROGRAMMABLE DELAY BLOCK
Timeout
WATCHDOG TIMER INPUT
Timeout
SERIAL BUS TIMING
Clock Frequency, f
Glitch Immunity, t
Bus Free Time, t
Start Setup Time, t
Start Hold Time, t
SCL Low Time, t
SCL High Time, t
SCL, SDA Rise Time, t
SCL, SDA Fall Time, t
Data Setup Time, t
Data Hold Time, t
NOTES
1
These are target specifications and subject to change.
2
At least one supply connected to VH or VPn must be >=3.0V
3
Logic inputs will accept input high voltages up to 5.5V even when device is operating at supply voltages below 5V.
4
Timing specifications are tested at logic levels of V
REV.PrJ 11/02
PRELIMINARY TECHNICAL DATA
1
2
o
o
, T
= -40
C to 85
A
IH
IH
PULLDOWN
IH
OL
SCLK
SW
BUF
SU;STA
HD;STA
LOW
HIGH
r
f
SU;DAT
HD;DAT
= 0.8V for a falling edge and V
IL
C, unless otherwise noted.)
Min
Typ
Max
440
10.5
12.5
14
10
12
20
2.4
4.5
V
-0.3
PU
0.4
1.2
2.0
20
20
2
10
2.0
0.8
-1
1
T B D
10
2.0
0.8
0.4
0
500
0
12.8
400
50
4.7
4.7
4
4.7
4
1000
300
250
300
IH
– 5 –
Units
Test Conditions/Comments
k
V
I
= 0
O H
V
I
=1 A
OH
A
2V<V
<7V
O H
V
V
(Pullup to VDDCAP or
PU
VPn)=2.7V, I
V
V
to VPn=6.0V, I
PU
V
VPU<=2.7V, I
V
I
=2mA
OL
V
I
=10mA
OL
V
I
=15mA
OL
mA
Total Sink Current
k
Internal pullup
mA
Current Load on any VPn pull-ups
(ie) total source current available
through any number of PDO pull-up
switches configured on to any one
A
V
=14.4V
PDO
V
Max. V
=5.5V
IN
V
Max. V
=5.5V
IN
A
V
= 5.5V
IN
A
V
= 0
IN
p F
A
If known logic state required
V
V
V
I
= -3.0mA
OUT
ms
16 programmable options on both
rising and falling edge
s
8 programmable timeout options
KHz
See Figure 8c
ns
See Figure 8c
µ s
See Figure 8c
µ s
See Figure 8c
µ s
See Figure 8c
µ s
See Figure 8c
µ s
See Figure 8c
ns
See Figure 8c
µ s
See Figure 8c
ns
See Figure 8c
ns
See Figure 8c
= 2.2V for a rising edge.
=1mA
OH
=0mA
OH
=1mA
OH

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