SMART Embedded Computing Penguin Edge MVME250 Series Installation And User Manual page 132

Programming Model
Table 7-1
CONFIG
ETSEC2
22
Protocol
ETSEC3
23
Protocol
BOOT ROM
24
Location
Host/Agent
25
Config
I/O Port
26
Select
DDR
27 SDRAM
TYPE
SerDes PLL
28 Time Out
Enable
132
POR Configuration Settings (continued)
CONFIG PINS
TSEC2_TXD0,
TSEC2_TXD7
UART_RTS0,
UART_RTS1
TSEC1_TXD[6:4],
TSEC1_TX_ER
LWE1/LBS1,
LA[18:19]
TSEC1_TXD[3:1],
TSEC2_TX_ER
TSEC2_TXD1
TRIG_OUT
CONFIG SELECTION
The eTSEC2 controller
operates using the
GMII protocol (or
10 RGMII, if configured in
reduced mode) if its not
configured to operate
in SGMII mode.
The eTSEC3 controller
operates using the
10 RGMII protocol if not
configured to operate
in SGMII mode.
On-chip boot ROM-SPI
011X configuration (x=0),
SDHC (x=1)
The processor acts as
the host/root complex
111 for all PCI-E/Serial
Rapid IO interfaces
(default).
PCI-E 1 (x1) (2.5
Gbps) - SerDes lane 0
PCI-E 2 (x1) (2.5
0010 Gbps) - SerDes lane 2
PCI-E 3 (x2) (2.5
Gbps) - SerDes lane 2-
3
DDR31.5 V. CKE low at
1
reset (default)
Disable PLL lock time-
out counter. The
power-on-reset
1 sequence waits
indefinitely for the
SerDes PLL to lock
(default).
MVME2502 Installation and Use (6806800R96L)
Programming Model
REMARKS