Xilinx Virtex-7 FPGA VC7215 Getting Started Manual page 38

12. The SuperClock-2 source code now needs to be added to the example ibert wrapper. In
the Sources window, double-click example_ibert_7series_gth_0 in the Design Sources
folder to open the Verilog code. Add the top level ports from top_scm2.v to the
module declaration, and instantiate the top_scm2 module in the example ibert wrapper
(Figure 1-29). Click File > Save File.
X-Ref Target - Figure 1-29
VC7215 Getting Started Guide
UG970 (Vivado Design Suite v2015.1) April 27, 2015
Figure 1-29: SuperClock-2 in the Example IBERT Wrapper
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Chapter 1: VC7215 IBERT Getting Started Guide
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