Creating The Gth Ibert Core - Xilinx Virtex-7 FPGA VC7215 Getting Started Manual

Creating the GTH IBERT Core

Vivado Design Suite 2015.1 is required to rebuild the designs shown here.
This section provides a procedure to create a single Quad GTH IBERT core with integrated
SuperClock-2 controller. The procedure assumes Quad 115 and 13.0 Gb/s line rate, but
cores for any of the GTH Quads with any supported line rate can be created following the
same series of steps.
For more details on generating IBERT cores, refer to Vivado Design Suite User Guide:
Programming and Debugging (UG908)
1. Start the Vivado Design Suite.
2. In the Vivado window, click the Manage IP icon highlighted in
New IP Location.
X-Ref Target - Figure 1-20
VC7215 Getting Started Guide
UG970 (Vivado Design Suite v2015.1) April 27, 2015
[Ref 3]
Figure 1-20: Initial Window, Vivado Design Suite
www.xilinx.com
Chapter 1: VC7215 IBERT Getting Started Guide
.
Figure 1-20, then select
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