Xilinx Virtex-7 FPGA VC7215 Getting Started Manual page 35

9. In the Clock Settings tab, select DIFF SSTL15 for the I/O Standard, enter J25 for P
Package Pin and J26 for N Package Pin (the FPGA pins that the system clock connects
to), and ensure the Frequency is set to 200.00
X-Ref Target - Figure 1-26
VC7215 Getting Started Guide
UG970 (Vivado Design Suite v2015.1) April 27, 2015
Chapter 1: VC7215 IBERT Getting Started Guide
Figure 1-26: Customize IP - Clock Settings
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(Figure 1-26). Press OK.
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