Extracting The Project Files - Xilinx Virtex-7 FPGA VC7215 Getting Started Manual

Extracting the Project Files

The Vivado project files required to run the IBERT demonstrations are located in
rdf0294-vc7215-ibert-2015-1.zip on the SD card provided with the VC7215 board.
They are also available online at the
The ZIP file contains these files:
• BIT files
20 BIT files, one for each of the board's 20 Quads
°
(vc7215_ibert_qxxx_325.bit)
• Probe files
20 probe files, one for each of the board's 20 QuadS (vc7215_qxxx_325.ltx)
°
• The complete project files
• TCL scripts
° add_scm2.tcl
° setup_scm2_325_00.tcl
The Tcl scripts are used to help merge the IBERT and SuperClock-2 source code (described
in Creating the GTH IBERT Core, page
325.00 MHz (described in
To copy the files from the Secure Digital memory card:
1. Connect the Secure Digital memory card labeled IBERT #1 to the host computer.
2. Locate the file rdf0294-vc7215-ibert-2015-1.zip on the Secure Digital memory
card.
3. Unzip the files to a working directory on the host computer.
VC7215 Getting Started Guide
UG970 (Vivado Design Suite v2015.1) April 27, 2015
Chapter 1: VC7215 IBERT Getting Started Guide
Virtex-7 FPGA VC7215 Characterization Kit
29) and to set up the SuperClock-2 module to run at
Setting Up Vivado Design Suite, page
www.xilinx.com
website.
16).
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