Xilinx Virtex-7 FPGA VC7215 Getting Started Manual page 41

16. When the Synthesized Design opens, select dbg_hub in the Netlist window, then select
the Debug Core Options tab in the Cell Properties window. Change
C_USER_SCAN_CHAIN* to 3
X-Ref Target - Figure 1-33
VC7215 Getting Started Guide
UG970 (Vivado Design Suite v2015.1) April 27, 2015
(Figure 1-33). Click File > Save Constraints.
Figure 1-33: Debug Core Options for dbg_hub
www.xilinx.com
Chapter 1: VC7215 IBERT Getting Started Guide
41
Send Feedback