Xilinx Virtex-7 FPGA VC7215 Getting Started Manual page 9

All GTH transceiver pins and reference clock pins are routed from the FPGA to a connector
pad which interfaces with Samtec BullsEye connectors.
pad. Figure 1-2
X-Ref Target - Figure 1-2
The SuperClock-2 module provides LVDS clock outputs for the GTH transceiver reference
clocks in the IBERT demonstrations.
SMA connectors on the clock module which can be connected to the reference clock cables.
The image in
Note:
board.
X-Ref Target - Figure 1-3
VC7215 Getting Started Guide
UG970 (Vivado Design Suite v2015.1) April 27, 2015
B shows the connector pinout.
Figure 1-2: A – GTH Connector Pad. B – GTH Connector Pinout
Figure 1-3
Figure 1-3 is for reference only and might not reflect the current revision of the
Figure 1-3: SuperClock-2 Module Output Clock SMA Locations
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Chapter 1: VC7215 IBERT Getting Started Guide
Figure 1-2 A shows the connector
shows the locations of the differential clock
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