Xilinx Virtex-7 FPGA VC7215 Getting Started Manual page 10

The four SMA pairs labeled CLKOUT provide LVDS clock outputs from the Si5368 clock
multiplier/jitter attenuator device on the clock module. The SMA pair labeled Si570_CLK
provides LVDS clock output from the Si570 programmable oscillator on the clock module.
The Si570 oscillator does not support LVDS output on the Rev B and earlier revisions of the
Note:
SuperClock-2 module.
For the GTH IBERT demonstration, the output clock frequencies are preset to 325.00 MHz.
For more information regarding the SuperClock-2 module, refer to HW-CLK-101-SCLK2
SuperClock-2 Module User Guide (UG770)
Attach the GTH Quad Connector
Before connecting the BullsEye cable assembly to the board, firmly secure the blue
elastomer seal provided with the cable assembly to the bottom of the connector housing if
it is not already inserted (see
Figure 1-4
Note:
X-Ref Target - Figure 1-4
VC7215 Getting Started Guide
UG970 (Vivado Design Suite v2015.1) April 27, 2015
Figure 1-4).
is for reference only and might not reflect the current version of the connector.
Figure 1-4: BullsEye Connector with Elastomer Seal
www.xilinx.com
Chapter 1: VC7215 IBERT Getting Started Guide
[Ref 2].
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