Part 6.4: Usb2.0 Interface - Alinx ZYNQ7000 FPGA User Manual

ETH_TXD2
ETH_TXD3
ETH_TXCTL
ETH_RXCK
ETH_RXD0
ETH_RXD1
ETH_RXD2
ETH_RXD3
ETH_RXCTL
ETH_MDC
ETH_MDIO

Part 6.4: USB2.0 Interface

There are 1 USB2.0 HOST interfaces on the AX7010 FPGA development
board. The USB2.0 transceiver uses a 1.8V, high-speed USB3320C-EZK chip
that supports the ULPI standard interface. ZYNQ's USB bus interface is
connected to the USB3320C-EZK transceiver for high-speed USB2.0 Host
mode and Slave mode data communication. The USB3320C's USB data and
control signals are connected to the IO port of the BANK501 on the PS side of
the ZYNQ chip. One 24MHz crystals provide clocks for the USB3320C.
The AX7010 FPGA development board provides users with two USB
interfaces, one is the Host USB port and the other is the Slave USB port. They
are a flat USB interface (USB Type A) and a micro USB interface (Micro USB),
which are convenient for users to connect different USB peripherals. Users can
switch between Host and Slave through J5 and J6 jumpers on the AX7010
FPGA development board. Table 6-4 shows the mode switching instructions:
J5,J6 Status
J5 and J6 installation
jumper caps
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ZYNQ FPGA Development Board AX7010 User Manual
PS_MIO19_501
PS_MIO20_501
PS_MIO21_501
PS_MIO22_501
PS_MIO23_501
PS_MIO24_501
PS_MIO25_501
PS_MIO26_501
PS_MIO27_501
PS_MIO52_501
PS_MIO53_501
USB Mode
HOST Mode FPGA Development board as the main device, USB
port to connect the mouse, keyboard, USB and other
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D10 Transmit data bit2
A17 Transmit data bit3
F14 Transmit enable signal
B17 RGMII Receive Clock
D11 Receive data Bit0
A16 Receive data Bit1
F15 Receive data Bit2
A15 Receive data Bit3
D13 Receive data valid signal
C10 MDIO
clock
C11 MDIO Management data
Instruction
slave peripherals
Management