Alinx ZYNQ7000 FPGA User Manual page 10

The development board is powered by +5V, and is converted into +3.3V,
+1.5V, +1.8V, +1.0V four-way power supply through four DC/DC power supply
chip TLV62130RGT. Each output current can be up to 3A. VCCIO power is
generated by one LDO SPX3819M5-3-3, and VCCIO is mainly used to power
the BANK35 of ZYNQ. By replacing other LDO chips, the BANK35's IO can be
adapted to different voltage standards. VTT and VREF Voltage required by
DDR3 are generated by 1.5V via TI's TPS51200. The functions of each power
distribution are shown in the following table below:
Power Supply
+1.0V
+1.5V
+1.8V
+3.3V
VREF, VTT
VCCIO
Because the power supply of the ZYNQ FPGA has the power-on
sequence requirements, in the circuit design, we have designed according to
the power requirements
+1.0V->+1.8V->+1.5 V->+3.3V->VCCIO, circuit design to ensure the normal
operation of the chip. Figure 3-2 shows the circuit design of the power supply:
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ZYNQ FPGA Development Board AX7010 User Manual
ZYNQ auxiliary voltage, ZYNQ PLL, ZYNQ BANK501, VCCIO,
ZYNQ VCCIO, Gigabit Ethernet, Serial Port, HDMI, RTC,
of the
Amazon Store: https://www.amazon.com/alinx
Function
ZYNQ Core Voltage
DDR3, ZYNQ Bank502
Ethernet, USB 2.0
FLASH,EEPROM SD Card
DDR3
ZYNQ Bank35
chip. The power-on sequence is