Alinx ZYNQ7000 FPGA User Manual page 26

samples of the clock.
Figure 6-4: The connection of the ZYNQ and GPHY chip
Figure 6-5: The GPHY chip on FPGA Board
The Gigabit Ethernet pin assignments are as follows：
Signal Name
ETH_GCLK
ETH_TXD0
ETH_TXD1
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ZYNQ FPGA Development Board AX7010 User Manual
ZYNQ Pin Name
PS_MIO16_501
PS_MIO17_501
PS_MIO18_501
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ZYNQ Pin Number
A19
E14
B18
Description
RGMII Transmit Clock
Transmit data bit0
Transmit data bit1