Part 6.2: Ddr3 Dram - Alinx ZYNQ7000 FPGA User Manual

Configure chip pin assignments:
Signal Name
QSPI_SCK
QSPI_CS
QSPI_D0
QSPI_D1
QSPI_D2
QSPI_D3

Part 6.2: DDR3 DRAM

The AX7010 FPGA development board is equipped with two
DDR3 chips
MT41J128M16HA-125
533MHz (data rate 1066Mbps), and two DDR3 memory systems are directly
connected to the memory interface of the BANK 502 of the ZYNQ Processing
System (PS). The specific configuration of DDR3 SDRAM is shown in Table
6-2.
Bit Number
U8,U9
The hardware design of DDR3 requires strict consideration of signal
integrity. We have fully considered the matching resistor/terminal resistance,
trace impedance control, and trace length control in circuit design and PCB
design to ensure high-speed and stable operation of DDR3.
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ZYNQ FPGA Development Board AX7010 User Manual
ZYNQ Pin Name
PS_MIO6_500
PS_MIO1_500
PS_MIO2_500
PS_MIO3_500
PS_MIO4_500
PS_MIO5_500
(total 4Gbit),
). The DDR3 SDRAM has a maximum operating speed of
Chip Model
H5TQ2G63FFR-RDC
Table 6-2: DDR3 SDRAM Configuration
Amazon Store: https://www.amazon.com/alinx
model
H5TQ2G63FFR
Capacity
128M x 16bit
ZYNQ Pin Number
A5
A7
B8
D6
B7
A6
SKHynix 2Gbit
(compatible
Factory
SKHynix
with