Part 4.2: Fpga Power System - Alinx ZYNQ7000 FPGA User Manual

Part 4.2: FPGA Power System

The power supply of the ZYNQ chip is divided into the PS system part and
the PL logic part, and the two parts of the power supply work independently.
The power supply of the PS system part and the power supply of the PL logic
part have a power-on sequence. The abnormal power-on sequence may cause
the ARM system and the FPGA system to not work properly.
The power supply for the PS section is VCCPINT, VCCPAUX, VCCPLL,
and PS VCCO. VCCPINT is the PS core power supply pin, connected to 1.0V;
VCCPAUX is the PS system auxiliary power supply pin, connected to 1.8V;
VCCPLL is the PS internal clock PLL power supply pin, also connected to 1.8V;
PS VCCO is BANK voltage, Including VCCO_MIO0, VCCO_MIO1 and
VCCO_DDR, depending on the connected peripherals, the connected power
supply will be different. On the AX7010 development board, VCC_MIO0 is
connected to 3.3V, VCCO_MIO1 is connected to 1.8V, and VCCO_DDR is
connected to 1.5V. The PS system requires that the power-up sequence be
VCCPINT first, then VCCPAUX and VCCPLL, and finally PS VCCO. The order
of power outages is reversed.
The power supply for the PL section is VCCINT, VCCBRAM, VCCAUX and
VCCO. VCCPINT is the FPGA core power supply pin, connected to 1.0V;
VCCBRAM is the power supply pin of the FPGA block RAM; connected to 1.0V;
VCCAUX is the FPGA auxiliary power supply pin, connected to 1.8V; VCCO is
the voltage of each BANK of PL, including BANK13, BANK34, BANK35, on the
AX7010 development board, the voltage of BANK is connected to 3.3V. The PL
system requires that the power-up sequence be VCCINT first, then VCCBRAM,
then VCCAUX, and finally VCCO. If VCCINT and VCCBRAM have the same
voltage, they can be powered up at the same time. The order of power outages
is reversed.
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ZYNQ FPGA Development Board AX7010 User Manual
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