Part 5.2: Pl System Clock Source - Alinx ZYNQ7000 FPGA User Manual

ZYNQ FPGA Development Board AX7010 User Manual
Figure 5-1: Active crystal oscillator to the PS section
Figure 5-2: 33.333Mhz active Crystal Oscillator on the FPGA board
PS Clock Pin Assignment
Signal Name ZYNQ Pin
PS_CLK E7

Part 5.2: PL system clock source

The AX7010 FPGA development board provides a single-ended 50MHz
PL system clock source with 3.3V supply. The crystal output is connected to
the FPGA global clock (MRCC), which can be used to drive user logic circuit
within the FPGA. The schematic diagram of the clock source is shown in Figure
5-3.
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