Measurement Computing Data Translation DT3034 User Manual page 93

Chapter 6
The conversion rate is determined by the frequency of the D/A output clock. The maximum
throughput rate in this mode is 500 kHz (500 kSamples/s) in 100 mV steps or 200 kHz
(200 kSamples/s) in full-scale steps. Refer to
clock.
To select waveform generation mode, use software to specify the following parameters:
• Set the dataflow to Continuous.
• Set WrapSingleBuffer to True to use a single buffer.
• Set the trigger source to any of the supported trigger sources. Refer to
Data Format and Transfer
Data from the host computer must use offset binary data encoding for analog output signals,
such as 0000 to represent 10 V, and FFFFh to represent +10 V. Using software, specify the
data encoding as binary.
The host computer transfers data as 32-bit words from one or more allocated circular buffers
in computer memory to the output FIFO on the board. DT3034 boards act as PCI slaves to the
host computer when performing analog output operations.
The host computer must pack two output samples (an even and an odd sample) into each
transfer to the DT3034 board. The even sample is written to the output FIFO first, followed by
the odd sample. If the analog output channel list contains two DACs, the even samples (0, 2, 4,
and so on) are written to channel entry 0 in the analog output channel list; the odd samples (1,
3, 5, and so on) are written to channel entry 1 in the analog output channel list. If the analog
output channel list contains one DAC, all the samples are written to the DAC, alternating
between even and odd samples.
Note that for continuously-paced analog output operations, the data from the circular buffers
in host computer memory can wrap multiple times. Data is output from each of the buffers on
the queue; when no more buffers are on the queue, the operation stops.
In waveform generation mode, the data from a single circular buffer is written once to the
output FIFO on the board (wrap mode is single); the board then continuously outputs the
data. That is, once all the data in the buffer is written to the output FIFO on the board, the host
computer is finished transferring data; the board recycles the data in the output FIFO without
using the bandwidth of the PCI bus or host processor, and the process repeats continuously
until you stop the operation.
92
information on the supported trigger sources.
page 88 for more information on the D/A output
page 89 for more