Measurement Computing Data Translation DT3034 User Manual page 87

Chapter 6
Using flags internally, the board determines whether the acquired samples are pre-trigger or
post-trigger samples. These flags are not transferred to the host computer. The host computer
can read the register on the board to determine where the post-trigger data starts. Note that
the host computer cannot read data directly from the board; the data must be transferred to
the host computer.
Using PCI bus mastering, the board transfers the analog input data to a 256 KB circular buffer,
which is dedicated to the hardware, in the host computer. The board treats this buffer as two
consecutive 128 KB blocks of memory.
Note: When you stop an analog input operation, a final block of 32 samples is transferred
even if less data is required. The host software ignores the extra samples.
The DT3034 Device Driver accesses the hardware circular buffer to fill user buffers that you
allocate in software. It is recommended that you allocate a minimum of two buffers for analog
input operations and add them to the subsystem queue using software. Data is written to the
queued input buffers continuously; when no more empty buffers are available on the queue,
the operation stops. The data is gap-free.
Error Conditions
DT3034 boards can report the following analog input error conditions to the host computer:
• A/D Over Sample – Indicates that the A/D sample clock rate is too fast. This error is
• Input FIFO Overflow – Indicates that the analog input data is not being transferred fast
• Host Block Overflow – Indicates that the host computer is not handling data from the
If any of these error conditions occurs, the board stops acquiring and transferring data to the
host computer.
Note: DT-Open Layers reports any of these errors as an overrun message.
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reported if a new A/D sample clock pulse occurs while the ADC is busy performing a
conversion from the previous A/D sample clock pulse. The host computer can clear this
error. To avoid this error, use a slower sampling rate.
enough from the Input FIFO across the PCI bus to the host computer. This error is
reported when the Input FIFO becomes full; the board cannot get access to the PCI bus
fast enough. The host computer can clear this error, but the error will continue to be
generated if the Input FIFO is still full. To avoid this error, close other applications that
may be running while you are acquiring data. If this has no effect, try using a computer
with a faster processor or reduce the sampling rate.
board fast enough. This error is reported if the board completes the transfer of a block of
input data to the circular buffer in the host computer before the host computer has
finished reading the last block of data. The host computer can clear this error. If you
encounter this error, try allocating more buffers or larger buffers.