loading the device driver
Windows 7
31
Windows Vista
31
Windows XP
30
logic-high level gate type
logic-low level gate type
,
low-edge gate type
98
120
low-level gate type
120
low-to-high pulse output
LV-Link
18
M
MaxDifferentialChannels
MaxExtClockDivider
119
MaxFrequency
119
MaxMultiScanCount
114
MaxRetriggerFreq
114
MaxSingleEndedChannels
Measure Foundry
18
measuring frequency
102
MinExtClockDivider
119
MinFrequency
119
MinRetriggerFreq
114
N
negative threshold trigger
number of
differential channels
115
gains
116
I/O channels
115
resolutions
116
scans per trigger
114
single-ended channels
voltage ranges
116
NumberOfChannels
115
NumberOfRanges
116
NumberOfResolutions
116
NumberOfSupportedGains
Nyquist Theorem
75
O
one-shot mode
105
one-shot pulse output
120
online help
59
operation modes
continuous digital input
continuously-paced scan mode
event counting
100
98
98
99
115
115
118
115
116
95
76
externally-retriggered scan mode
frequency measurement
one-shot pulse output
rate generation
103
repetitive one-shot pulse output
single-value analog input
single-value analog output
single-value digital I/O
software-retriggered scan mode
waveform generation
91
orderly stop
analog input
76
analog output
90
output clock sources
external D/A output clock
internal D/A output clock
,
,
,
output FIFO
16
90
91
92
output FIFO counter
91
output FIFO underflow error
output pulses
120
output ranges
88
outputting pulses
continuously
103
one-shot
105
repetitive one-shot
107
P
PCI bus master
86
PCI bus slave
92
physical specifications
149
pin assignments
DT740 screw terminal panel J1 connector
DT740 screw terminal panel J2 connector
J1 connector
154
J2 connector
156
ports
94
positive threshold trigger
post-trigger acquisition mode
power specifications
149
pre-trigger acquisition mode
pseudo-differential inputs
pulse output
duty cycle
99
one-shot
105
rate generation
103
repetitive one-shot
107
types
99
pulse train output
103
pulse width
99
78
102
105
107
76
90
94
77
88
88
93
,
43
158
,
44
159
118
,
81
113
,
82
113
45
Index
173
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