Alinx AX7050 User Manual page 34

transmission clock is 25Mhz. Both the receive clock E_RXC and the transmit
clock E_TXC are provided by the PHY chip, and data is sampled on the rising
edge of the clock..
U6
FPGA
Spartan7
Figure 3-2-1: Gigabit Ethernet Interface Schematic
Figure 3-3-2: Gigabit Ethernet interface on the Carrier Board
Ethernet PHY1 Chip Pin assignments are as follows：
Net Name
E_GTXC
E_TXD0
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Spartan-7 FPGA Development Board AX7050 User Manual
FPGA Pin Number
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RTL8211EG
E_TXD[3:0]
TXD[3:0]
E_TXEN
TXEN
E_GTXC
GTX_CLK
E_TXC
TX_CLK
E_RXD[3:0]
RXD[3:0]
E_RXDV
RXDV
E_RXC
RXCLK
E_MDIO
MDIO
E_MDC
MDC
25Mhz
Cystal
F19
E19
U12
MDI[3:0]+/-
LED0
LED1
Description
RGMII Transmit Clock
Transmit Data bit0