Alinx AX7050 User Manual page 16

Spartan-7 FPGA Development Board AX7050 User Manual
U1
U5
Data[31:16] DDR3
(MT41J256M16
HA)
FPGA BANK
34/35
Addr/control
U6
DDR3
Data[15:0]
(MT41J256M16
HA)
Figure 2-4-1: The DDR3 DRAM Schematic
Figure 2-4-2: The DDR3 on the Core Board
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