Part 2.4: Ddr3 Dram - Alinx AX7050 User Manual

Reserved Differential Clock Pin Assignment

Part 2.4: DDR3 DRAM

The FPGA core board AC7050 is equipped with two Micron 4Gbit (512MB)
DDR3 chips,
MT41K256M16HA-125). DDR bus width is a total of 32bit. The DDR3 SDRAM
has a maximum operating speed of 333.3MHz (data rate 667Mbps). The DDR3
memory system is directly connected to the memory interface of the BANK 34
and BANK35 of the FPGA. The specific configuration of DDR3 SDRAM is
shown in Table 2-4-1.
Bit Number
U5,U6
The hardware design of DDR3 requires strict consideration of signal
integrity. We have fully considered the matching resistor/terminal resistance,
trace impedance control, and trace length control in circuit design and PCB
design to ensure high-speed and stable operation of DDR3.
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Spartan-7 FPGA Development Board AX7050 User Manual
Signal Name
SYS_CLK_P
SYS_CLK_N
model is MT41J256M16HA-125
Chip Model
MT41J256M16HA-125
Table 2-4-1: DDR3 SDRAM Configuration
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FPGA PIN
AA6
AB6
(compatible
Capacity Factory
256M x 16bit
with
Micron