Alinx AX7050 User Manual page 24

Board to Board Connectors CON1
The 80-pin board to board connectors CON1, which is used to connect the
normal IO of FPGA (which contains 6 pairs of differential interface IO, can be
used as LVDS data communication), the default IO level is 3.3V. The pin
assignment of the CON1 expansion port is shown in Table 2-9-1.
Pin Assignment of Board to Board Connectors CON1
CON1 Net
PIN Name
PIN1 B15_L10_P
PIN3 B15_L10_N
PIN5 B15_L7_P
PIN7 B15_L7_N
PIN9 GND
PIN11 B15_L9_P
PIN13 B15_L9_N
PIN15 B15_L8_P
PIN17 B15_L8_N
PIN19 GND
PIN21 B16_L20_P
PIN23 B16_L20_N
PIN25 B16_L19_P
PIN27 B16_L19_N
PIN29 GND
PIN31 B16_L15_P
PIN33 B16_L15_N
PIN35 B16_L13_P
PIN37 B16_L13_N
PIN39 GND
PIN41 B16_L23_N
PIN43 B16_L23_P
PIN45 GND
PIN47 B16_L21_N
PIN49 B16_L21_P
PIN51 GND
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Spartan-7 FPGA Development Board AX7050 User Manual
FPGA Input/
PIN Output
E22
D22
B21
B22
- Ground
D21
C22
D20
C20
- Ground
C19
B19
D18
C18
- Ground
D16
C17
C15
C16
- Ground
A20
B20
- Ground
A19
A18
- Ground
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CON1
PIN
I/O PIN2 B15_L11_P
I/O PIN4 B15_L11_N
I/O PIN6 B15_L20_P
I/O PIN8 B15_L20_N
PIN10
I/O PIN12 B15_L12_P
I/O PIN14 B15_L12_N
I/O PIN16 B16_L24_P
I/O PIN18 B16_L24_N
PIN20
I/O PIN22 B16_L22_P
I/O PIN24 B16_L22_N
I/O PIN26 B16_L16_P
I/O PIN28 B16_L16_N
PIN30
I/O PIN32 B16_L6_P
I/O PIN34 B16_L6_N
I/O PIN36 B16_L4_P
I/O PIN38 B16_L4_N
PIN40
I/O PIN42 B16_IO0
I/O PIN44 B16_L17_N
PIN46 B16_L17_P
I/O PIN48 B16_L7_N
I/O PIN50 B16_L7_P
PIN52
Net FPGA
Name PIN
F21
F22
G21
G22
GND -
F19
F20
E19
D19
GND -
E17
E18
E15
E16
GND -
G14
F15
F13
F14
GND -
G13
A14
B14
C13
D13
GND -
Input/
Output
I/O
I/O
I/O
I/O
Ground
I/O
I/O
I/O
I/O
Ground
I/O
I/O
I/O
I/O
Ground
I/O
I/O
I/O
I/O
Ground
I/O
I/O
I/O
I/O
I/O
Ground