Alinx AX7050 User Manual page 25

PIN53 B16_L18_N
PIN55 B16_L18_P
PIN57 GND
PIN59 B16_L14_N
PIN61 B16_L14_P
PIN63 GND
PIN65 B16_L9_N
PIN67 B16_L9_P
PIN69 GND
PIN71 B16_L8_N
PIN73 B16_L8_P
PIN75 GND
PIN77 B16_L10_N
PIN79 B16_L10_P
The pins of B16_L23_P/N, B16_L21_P/N, B16_L18_P/N, B16_L14_P/N,
B16_L9_P/N and B16_L8_P/N are differentially derived on the PCB and can be
used as high-speed LVDS data communication.
Figure 2-9-1: Board to Board Connectors CON1 on the Core Board
Board to Board Connectors CON2
The 80-pin board to board connectors CON1, which is used to connect to
+5V power supply, JTAG interface signal and the normal IO of FPGA (which
contains 6 pairs of differential interface IO, can be used as LVDS data
communication), the default IO level is 3.3V. The pin assignment of the CON2
expansion port is shown in Table 2-9-2
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Spartan-7 FPGA Development Board AX7050 User Manual
A17
A16
- Ground
B16
B15
- Ground
A13
B13
- Ground
A12
A11
- Ground
C11
C10
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I/O PIN54 B16_L11_P
I/O PIN56 B16_L11_N
PIN58 B16_L12_P
I/O PIN60 B16_L12_N
I/O PIN62 B16_L5_N
PIN64
I/O PIN66 B16_L5_P
I/O PIN68 B16_L3_N
PIN70 B16_L3_P
I/O PIN72 B16_L1_N
I/O PIN74 B16_L1_P
PIN76
I/O PIN78 B16_L2_N
I/O PIN80 B16_L2_P
D14
D15
D12
C12
E12
GND -
F12
D11
E11
F11
G11
GND -
F10
G10
I/O
I/O
I/O
I/O
I/O
Ground
I/O
I/O
I/O
I/O
I/O
Ground
I/O
I/O