Part 3.2: Gigabit Ethernet Interface - Alinx AX7050 User Manual

 4 independent buttons
 4 user LED lights

Part 3.2: Gigabit Ethernet Interface

The AX7050 FPGA development board provides users with one-channel
Gigabit network communication service through the Realtek RTL8211EG
Ethernet PHY chip. The RTL8211EG chip supports 10/100/1000 Mbps network
transmission rate and data communicates with the FPGA through the RGMII
interface. RTL8211EG supports MDI/MDX adaptation, various speed
adaptations, Master/Slave adaptation, and support for MDIO bus for PHY
register management.
The RTL8211EG will detect the level status of some specific IOs to
determine their working mode after powered on. Table 3-1-1 describes the
default setup information after the GPHY chip is powered on.
Configuration Pin
PHYAD[2:0]
SELRGV
AN[1:0]
RX Delay
TX Delay
MODE
When the network is connected to Gigabit Ethernet, the data
transmission of FPGA and PHY chip RTL8211EG is communicated through the
RGMII bus, the transmission clock is 125Mhz. The receive clock E_RXC is
provided by the PHY chip, the transmit clock E_GTXC is provided by the FPGA,
and the data is sampled on the rising edge of the clock.
When the network is connected to 100M Ethernet, the data transmission of
FPGA and PHY chip RTL8211EG is communicated through the MII bus, the
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Spartan-7 FPGA Development Board AX7050 User Manual
Instructions
MDIO/MDC Mode PHY Address
3.3V, 2.5V, 1.5/1.8V voltage
selection
Auto-negotiation configuration
RX clock 2ns delay
TX clock 2ns delay
RGMII or GMII selection
Table 3-2-1: PHY chip default configuration value
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Configuration value
PHY Address 011
3.3V
(10/100/1000M) adaptive
Delay
Delay
RGMII