Pwm Mode - Abov MC80F0304 User Manual

MC80F0304/08/16

13.6 PWM Mode

Modulation) functions which shared with Timer1 or Timer3. The MC80F0304/0308/0316 has high speed PWM (Pulse Width resolution.
In PWM mode, R10 / PWM1O or R11 / PWM3O pin output up Frequency
to a 10-bit resolution PWM output. These pins should be config- Resolution T1CK[1:0] T1CK[1:0] T1CK[1:0]
ured as a PWM output by setting "1" bit PWM1OE and PWM3OE in PSR0 register. = 00(250nS) = 01(500nS) = 10(2uS)
10-bit 3.9kHz 0.98kHz 0.49kHz
PWM Period Register) and T1PWHR[3:2] (bit3,2 of T1 PWM The period of the PWM1 output is determined by the T1PPR (T1 9-bit 7.8kHz 1.95kHz 0.97kHz
High Register) and the duty of the PWM output is determined by 8-bit 15.6kHz 3.90kHz 1.95kHz
the T1PDR (T1 PWM Duty Register) and T1PWHR[1:0] (bit1,0 of T1 PWM High Register). 7-bit 31.2kHz 7.81kHz 3.90kHz
The period of the PWM3 output is determined by the T3PPR (T3 PWM Period Register) and T3PWHR[3:2] (bit3,2 of T3 PWM Table 13-3 PWM Frequency vs. Resolution at 4MHz
High Register) and the duty of the PWM output is determined by The bit POL of TM1 or TM3 decides the polarity of duty cycle.
the T3PDR (T3 PWM Duty Register) and T3PWHR[1:0] (bit1,0 of T3 PWM High Register). If the duty value is set same to the period value, the PWM output
The user writes the lower 8-bit period value to the T1(3)PPR( and is determined by the bit POL (1: High, 0: Low). And if the duty
the higher 2-bit period value to the T1(3)PWHR[3:2]. And writes value is set to "00 H ", the PWM output is determined by the bit
duty value to the T1(3)PDR and the T1(3)PWHR[1:0] same way. POL (1: Low, 0: High).
The T1(3)PDR is configured as a double buffering for glitchless It can be changed duty value when the PWM output. However the changed duty value is output after the current period is over. And
the master to the slave when the period data matched to the count- PWM output. In Figure 13-18 , the duty data is transferred from it can be maintained the duty value at present output when
ed value. (i.e. at the beginning of next duty cycle) absolute duty time is not changed in varying frequency. But the changed only period value shown as Figure 13-20 . As it were, the
PWM1(3) Period = [PWM1(3)HR[3:2]T1(3)PPR] X changed period value must greater than the duty value.
Source Clock
PWM1(3) Duty = [PWM3HR[1:0]T1(3)PDR] X Source Note: If changing the Timer1 to PWM function, it should be stop
Clock If user writes register values while timer is in operation, these reg- the timer clock firstly, and then set period and duty register value.
ister could be set with certain values.
The relation of frequency and resolution is in inverse proportion. Ex) Sample Program @4MHz 2uS
Table 13-3 shows the relation of PWM frequency vs. resolution.
If it needed more higher frequency of PWM, it should be reduced LDM LDM T1PPR,#199 TM1,#1010_1000b ; Set Clock & PWM3E ; Period :400uS=2uSX(199+1)
LDM T1PDR,#99 ; Duty:200uS=2uSX(99+1)
LDM LDM PWM1HR,00H TM1,#1010_1011b ; Start timer1
74 November 4, 2011 Ver 2.12