Power Saving Operation; Sleep Mode - Abov MC80F0304 User Manual

MC80F0304/08/16

19. POWER SAVING OPERATION

power-down mode, power consumption is reduced considerably. The MC80F0304/0308/0316 has two power-down modes. In Saving Mode. SLEEP mode is entered by the SSCR register to and SLEEP mode. Table 19-1 shows the status of each Power
For applications where power consumption is a critical factor, de- "0Fh"., and STOP mode is entered by STOP instruction after the
vice provides two kinds of power saving functions, STOP mode SSCR register to "5Ah".

19.1 Sleep Mode

In this mode, the internal oscillation circuits remain active. is released by Reset or interrupt. To be released by interrupt, in-
Oscillation continues and peripherals are operate normally but terrupt should be enabled before SLEEP mode.
CPU stops. Movement of all peripherals is shown in Table 19-1. SLEEP mode is entered by setting the SSCR register to "0Fh". It
W W W W W W W W
7 6 5 4 3 2 1 0
SSCR ADDRESS: 0F5 INITIAL VALUE: 0000 0000 H B
H : STOP mode Power Down Control 5A
H 0F : SLEEP mode
NOTE : To get into STOP mode, SSCR must be set to 5AH just before STOP instruction execution.
To get into SLEEP mode, SSCR must be set to 0FH. At STOP mode, Stop & Sleep Control Register (SSCR) value is cleared automatically when released.
Figure 19-1 STOP and SLEEP Control Register
Release the SLEEP mode When exit from SLEEP mode by reset, enough oscillation stabi-
lizing time is required to normal operation. Figure 19-3 shows
The exit from SLEEP mode is hardware reset or all interrupts. Reset re-defines all the Control registers but does not change the the timing diagram. When released from the SLEEP mode, the
on-chip RAM. Interrupts allow both on-chip RAM and Control Basic interval timer is activated on wake-up. It is increased from
registers to retain their values. tion. Therefore, before SLEEP instruction, user must be set its 00 until FF H . The count overflow is set to start normal opera- H
If I-flag = 1, the normal interrupt response takes place. If I-flag = relevant prescaler divide ratio to have long enough time (more
0, the chip will resume execution starting with the instruction fol- than 20msec). This guarantees that oscillator has started and sta-
vice routine. (refer to Figure 19-4 ) lowing the SLEEP instruction. It will not vector to interrupt ser- bilized. By interrupts, exit from SLEEP mode is shown in Figure
19-2 . By reset, exit from SLEEP mode is shown in Figure 19-3 .
102 November 4, 2011 Ver 2.12