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Abov MC80F0304 User Manual

8-bit single-chip microcontrollers
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ABOV SEMICONDUCTOR
8-BIT SINGLE-CHIP MICROCONTROLLERS
MC80F0304/0308/0316
MC80C0304/0308/0316
User's Manual
(Ver. 2.12)

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  • Page 1 ABOV SEMICONDUCTOR 8-BIT SINGLE-CHIP MICROCONTROLLERS MC80F0304/0308/0316 MC80C0304/0308/0316 User’s Manual (Ver. 2.12)
  • Page 2 ABOV Semiconductor reserves the right to make changes to any information here in at any time without notice. The information, diagrams and other data in this manual are correct and reliable; however, ABOV Semiconductor is in no way responsible for any violations of patents or other rights of the third party generated by the use of this manual.
  • Page 3 MC80F0304/08/16 REVISION HISTORY VERSION 2.12 (November 4, 2011) This Book Logo is changed. The dimensions of 28 SOP package outline drawing is fixed. VERSION 2.11 (May 14, 2008) Corrected Stack End Address to 0100 at Figure 8-4 on page 34.
  • Page 4 VERSION 1.4 (APR. 2006) Correct SIO Block diagram, Timing and usage. VERSION 1.3 (MAR. 2006) The company name, MagnaChip Semiconductor Ltd. changed to ABOV Semiconductor Co.,Ltd.. Add 28 SOP package type. VERSION 1.2 (OCT. 2005) Add notification that the DAA, DAS decimal adjust instructions are not supported.

  • Page 5: Table Of Contents

    Sequence to enter ISP mode/user mode ..124 16-bit Timer / Counter Mode ......65 ACK mode ............. 124 8-bit Compare Output (16-bit) ......67 Reference ISP Circuit Diagram and ABOV Sup- 8-bit Capture Mode ..........67 plied ISP Board ..........124 16-bit Capture Mode ........72 A.
  • Page 6 MC80F0304/08/16 B. MASK ORDER SHEET(MC80C0304) ....x D. MASK ORDER SHEET(MC80C0316) .... xii C. MASK ORDER SHEET(MC80C0308) ....xi November 4, 2011 Ver 2.12...

  • Page 7: Overview

    1. OVERVIEW 1.1 Description The MC80F0304/0308/0316 is advanced CMOS 8-bit microcontroller with 4K/8K/16K bytes of FLASH. This is a powerful microcontrol- ler which provides a highly flexible and cost effective solution to many embedded control applications. This provides the following features : 4K/8K/16K bytes of FLASH, 512 bytes of RAM, 8/16-bit timer/counter, watchdog timer, 10-bit A/D converter, 8-bit Serial Input/Output, UART, buzzer driving port, 10-bit PWM output and on-chip oscillator and clock circuitry.

  • Page 8: Development Tools

    • Oscillator Type - Avalilable Pb free package - Crystal 1.3 Development Tools The MC80F0304/0308/0316 is supported by a full-featured mac- ro assembler, an in-circuit emulator CHOICE-Dr. and OTP programmers. There are two different type of programmers such as single type and gang type. Macro assembler operates under the MS-Windows 95 and upversioned Windows OS.

  • Page 9: Ordering Information

    MC80F0304/08/16 1.4 Ordering Information Device name MASK ROM FLASH ROM Package MC80C0316B 16K bytes 32PDIP MC80C0316D32 16K bytes 32SOP MASK version 512bytes MC80C0316G 16K bytes 28SKDIP MC80C0316D 16K bytes 28SOP MC80C0308B 8K bytes 32PDIP MC80C0308D32 8K bytes 32SOP 512bytes MC80C0308G...

  • Page 10: Block Diagram

    MC80F0304/08/16 2. BLOCK DIAGRAM Accumulator Stack Pointer Data Memory Program RESET System controller Memory System 8-bit Basic Data Table Clock Controller Interval Interrupt Controller Timer Timing generator Clock Generator Instruction Decoder 10-bit 8-bit High Buzzer Timer/ Speed Watch-dog SIO/UART Driver...

  • Page 11: Pin Assignment

    MC80F0304/08/16 3. PIN ASSIGNMENT 32PDIP R04/AN4 / EC0 / RXD R03 / AN3 / INT2 R05 / AN5 / T0O / TXD R02 / AN2 / SOUT R06 / AN6 / T2O / ACLK R01 / AN1 / SI R07 / AN7 / EC1...

  • Page 12: Package Drawing

    MC80F0304/08/16 4. PACKAGE DRAWING 28 SKINNY DIP unit: inch TYP 0.300 1.375 0.300 1.355 0.275 0.021 0 ~ 15° 0.055 0.015 TYP 0.100 0.045 November 4, 2011 Ver 2.12...
  • Page 13 MC80F0304/08/16 28 SOP unit: millimetres 5 ~ 15° 17.90 GAUGE PLANE SEATING PLANE 0.51 1.27 0 ~ 8° 0.31 1.27 BSC 5 ~ 15° 0.40 1.40 REF 1. 17.90 dimension does not include mold FLASH, protrusions or gate burrs. Mold FLASH, protrusions or gate burrs shall not exceed 0.15mm per end.
  • Page 14 MC80F0304/08/16 unit: inch 32 PDIP TYP 0.600 1.665 0.550 1.645 0.530 0.022 0 ~ 15° 0.065 0.015 TYP 0.100 0.045 November 4, 2011 Ver 2.12...
  • Page 15 MC80F0304/08/16 32 SOP unit: milimeter 21.30 21.20 0 ~ 8° 0.45 0.95 0.35 TYP 1.27 0.55 November 4, 2011 Ver 2.12...

  • Page 16: Pin Function

    MC80F0304/08/16 5. PIN FUNCTION : Supply voltage. in Table 5-2 : Circuit ground. RESET: Reset the MCU. Port pin Alternate function : Input to the inverting oscillator amplifier and input to the in- AVref ( External Analog Reference Pin ) AN0 ( Analog Input Port 0 ) ternal main clock operating circuit.
  • Page 17 MC80F0304/08/16 Pin No. Function PIN NAME In/Out First Second Third Forth Supply voltage Circuit ground Input only port RESET (R35) Reset signal input Normal I/O Port (R33) Oscillation Input Normal I/O Port (R34) Oscillation Output R00 (INT3/SCK) External Interrupt 3...

  • Page 18: Port Structures

    MC80F0304/08/16 6. PORT STRUCTURES R13~R16,R20~R22,R27 R01 (AN1 / SI) Pull-up Pull-up Pull-up Reg. Pull-up Reg. Open Drain Reg. Open Drain Reg. Data Reg. Data Reg. Direction Reg. Direction Reg. Data Bus Data Bus AN[1] ADEN & ADS[3:0] (ADCM) Noise Filter...
  • Page 19 MC80F0304/08/16 R04 (AN4 / EC0 / RXD) R02 (AN2 / SOUT) Pull-up Pull-up Pull-up Pull-up Reg. Reg. Open Drain Open Drain Reg. Reg. Data Reg. Data Reg. Direction SOUT Reg. SO_EN(SIOM) Data Bus Direction Reg. Data Bus AN[1] ADEN & ADS[3:0]...
  • Page 20 MC80F0304/08/16 R06 (AN6 / T2O / ACLK) R05 (AN5 / T0O / TXD) Pull-up Pull-up Pull-up Pull-up Reg. Reg. Open Drain Open Drain Reg. Reg. Data Reg. Data Reg. T0OE(PSR1.0) T2OE(PSR1.1) TXE(ASIMR.7) Direction Direction Reg. Reg. Data Bus Data Bus...
  • Page 21 MC80F0304/08/16 (Crystal or Ceramic Resonator) R33 (X ), R34 (X Pull-up Pull-up Reg. Open Drain Reg. STOP Data Reg. Direction Reg. / R33 MAIN CLOCK Data Bus IN4MCLK IN2MCLK IN4MCLKXO IN2MCLKXO CLOCK option (Configuration option bit) (External RC or R oscillation)

  • Page 22: Electrical Charace Teristics

    MC80F0304/08/16 7. ELECTRICAL CHARACE TERISTICS 7.1 Absolute Maximum Ratings Supply voltage............-0.3 to +6.0 V ....................10 mA Storage Temperature ..........-65 to +150 °C Maximum current (ΣI ) ..........160 mA Voltage on any pin with respect to Ground (V Maximum current (ΣI )...........80 mA...

  • Page 23: Dc Electrical Characteristics

    MC80F0304/08/16 7.4 DC Electrical Characteristics =-40~85°C, V =5.0V, V =0V) Specifications Parameter Symbol Condition Unit Min. Typ. Max. , RESET 0.8 V 0.8 V Input High Voltage Hysteresis Input 0.7 V Normal Input , RESET 0.2 V Input Low Voltage 0.2 V...

  • Page 24: Ac Characteristics

    INT3 INT2, EC0, Figure 7-1 Timing Chart 7.6 Typical Characteristics (MC80F0304/08/16) These graphs and tables provided in this section are for design specified range. guidance only and are not tested or guaranteed. The data presented in this section is a statistical summary of data In some graphs or tables the data presented are out- collected on units from different lots over a period of time.
  • Page 25 MC80F0304/08/16 Operating Area Normal Operation (MHz) Ta= 25°C −V Ta=25°C (mA) =12MHz STOP Mode SLEEP Mode −V −V STOP SLEEP Ta=25°C Ta=25°C (μA) (mA) = 12MHz RC-WDT in Stop Mode −V RCWDT (μA) Ta=25°C = 50uS RCWDT November 4, 2011 Ver 2.12...
  • Page 26 MC80F0304/08/16 −V −V (mA) (mA) -25°C -25°C 25°C 25°C 85°C 85°C −V −V −V Hysteresis input Normal input , RESET =4kHz =4kHz =4MHz Ta=25°C Ta=25°C Ta=25°C −V −V −V Hysteresis input Normal input , RESET =4kHz =4kHz =4MHz Ta=25°C Ta=25°C Ta=25°C...
  • Page 27 Note: The external RC oscillation frequencies of the above are provided for design guidance only and not tested MC80F0304/0308/0316 may be different from that of the or guaranteed. The user needs to take into account that the MC80C0304/0308/0316. There may be the difference be- external RC oscillation frequencies generated by the same tween package types(PDIP, SOP, SKDIP).

  • Page 28: Typical Characteristics (Mc80C0304/08/16)

    MC80F0304/08/16 Note: The internal 4MHz oscillation frequencies shown in Typical Internal 4MHz above are provided for design guidance only and not tested Frequency vs V or guaranteed. The user needs to take into account that the internal oscillation of the MC80F0308 may show different (MHz) Ta = 25°C...
  • Page 29 MC80F0304/08/16 Operating Area Normal Operation (MHz) Ta= 25°C −V Ta=25°C (mA) =12MHz STOP Mode SLEEP Mode −V −V STOP SLEEP Ta=25°C Ta=25°C (μA) (mA) = 12MHz November 4, 2011 Ver 2.12...
  • Page 30 MC80F0304/08/16 −V −V (mA) (mA) -25°C -25°C 25°C 25°C 85°C 85°C −V −V −V Hysteresis input Normal input , RESET =4kHz =4kHz =4MHz Ta=25°C Ta=25°C Ta=25°C −V −V −V Hysteresis input Normal input , RESET =4kHz =4kHz =4MHz Ta=25°C Ta=25°C Ta=25°C...
  • Page 31 MC80F0304/08/16 Note: The internal 4MHz oscillation frequencies shown in above are provided for design guidance only and not tested or guaranteed. The user needs to take into account that the Typical Internal 4MHz internal oscillation of the MC80C0104 or MC80C0204 may...

  • Page 32: Memory Organization

    MC80F0304/08/16 8. MEMORY ORGANIZATION The MC80F0304/0308/0316 has separate address spaces for Pro- gram memory and Data Memory. 4K bytes program memory can Data memory can be read and written to up to 256 bytes including the stack area. only be read, not written to.
  • Page 33 MC80F0304/08/16 V G B H RESET VALUE: 00 CARRY FLAG RECEIVES NEGATIVE FLAG CARRY OUT OVERFLOW FLAG ZERO FLAG SELECT DIRECT PAGE INTERRUPT ENABLE FLAG when G=1, page is selected to “page 1” BRK FLAG HALF CARRY FLAG RECEIVES CARRY OUT FROM BIT 1 OF...

  • Page 34: Program Memory

    MC80F0304/08/16 At execution of At acceptance At execution At execution a CALL/TCALL/PCALL of interrupt of RET instruction of RET instruction 01FF Push 01FF 01FF 01FF 01FE down 01FE Push down 01FE 01FE 01FD 01FD 01FD 01FD 01FC 01FC 01FC 01FC...
  • Page 35 MC80F0304/08/16 program byte length by using 2 bytes PCALL instead of 3 bytes 0FFFB for External Interrupt 1, 0FFFC and 0FFFD for Ex- CALL instruction. If it is frequently called, it is more useful to ternal Interrupt 0, etc. save program byte length.
  • Page 36 MC80F0304/08/16 Address Program Memory PCALL Area Memory Address 0FFC0 0FF00 TCALL 15 TCALL 14 TCALL 13 TCALL 12 TCALL 11 TCALL 10 TCALL 9 TCALL 8 PCALL Area (256 Bytes) TCALL 7 TCALL 6 TCALL 5 TCALL 4 TCALL 3...

  • Page 37: Data Memory

    When returning from the processing routine, executing the sub- routine return instruction [RET] restores the contents of the pro- The MC80F0304/0308/0316 has 512 × 8 bits for the user memory gram counter from the stack; executing the interrupt return (RAM). RAM pages are selected by RPR (See Figure 8-9 ).
  • Page 38 MC80F0304/08/16 Initial Value Addressing Address Register Name Symbol Mode 7 6 5 4 3 2 1 0 00C0 R0 port data register 0 0 0 0 0 0 0 0 byte, bit 00C1 R0 port I/O direction register R0IO 0 0 0 0 0 0 0 0...
  • Page 39 MC80F0304/08/16 Initial Value Addressing Address Register Name Symbol Mode 7 6 5 4 3 2 1 0 00DB Timer 3 PWM high register T3PWHR - - - - 0 0 0 0 byte 00E0 Buzzer driver register BUZR 1 1 1 1 1 1 1 1...
  • Page 40 MC80F0304/08/16 The ‘byte, bit’ means registers are controlled by both bit and byte manipulation instruction. Caution) The R/W register except T1PDR and T3PDR are both can be byte and bit manipulated. The ‘byte’ means registers are controlled by only byte manipulation instruction. Do not use bit manipulation instruction such as SET1, CLR1 etc.

  • Page 41: Addressing Mode

    MC80F0304/08/16 Bit 7 Address Name Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0E3H SIOR SIO Data Shift Register 0E6H ASIMR PS01 PS00 ISRM 0E7H ASISR OVE0 0E8H BRGCR0 TPS02 TPS01 TPS00 MLD03 MLD02...
  • Page 42 MC80F0304/08/16 Immediate Addressing → #imm ;A ←RAM[35H] C535 In this mode, second byte (operand) is accessed as a data imme- diately. Example: data À 0435 #35H data → þ MEMORY 0E550H 0E551H A+35H+C → Absolute Addressing → !abs When G-flag is 1, then RAM address is defined by 16-bit address Absolute addressing sets corresponding memory data to Data, i.e.
  • Page 43 MC80F0304/08/16 ;A ←ROM[135H] 983501 !0135H À data 135H data data → Ã þ → À data+1 → data 0F100H þ 0F101H address: 0135 0F102H X indexed direct page (8 bit offset) → dp+X This address value is the second byte (Operand) of command plus Indexed Addressing the data of X-register.
  • Page 44 MC80F0304/08/16 D500FA !0FA00H+Y 1625 [25H+X] 0F100H þ 0F101H À 0E005H 0F102H 0FA00H+55H=0FA55H þ 25 + X(10) = 35H 0E005H data À 0FA55H data data → Ã 0FA00H Ã A + data + C → Indirect Addressing Y indexed indirect → [dp]+Y Direct page indirect →...
  • Page 45 MC80F0304/08/16 1F25E0 [!0C025H] PROGRAM MEMORY 0E025H 0E026H À jump to address 0E30AH þ 0E725H NEXT 0FA00H November 4, 2011 Ver 2.12...

  • Page 46: I/O Ports

    MC80F0304/08/16 9. I/O PORTS The MC80F0304/0308/0316 has three ports (R0, R1 and R3). These ports pins may be multiplexed with an alternate function for the peripheral features on the device. All port can drive max- WRITE “55 ” TO PORT R0 DIRECTION REGISTER imum 20mA of high current in output low state, so it can directly drive LED device.

  • Page 47: R1 And R1Io Register

    MC80F0304/08/16 counter input 0 (EC0), timer 0 output (T0O), timer 2 output (T2O) and event counter input 1 (EC1). When the alternate func- Port Pin Alternate Function tion is selected by writing “1” in the corresponding bit of PSR0 or PSR1, port pin can be used as a corresponding alternate fea-...

  • Page 48: R2 And R2Io Register

    MC80F0304/08/16 ADDRESS: 0F8 RESET VALUE: 0000 0000 ADDRESS: 0C2 R1 Data Register RESET VALUE: 00 PSR0 PWM3OE PWM1OE EC1E EC0E INT3E INT2E INT1E INT0E R17 R16 R15 R14 R13 R12 R11 R10 Port / INT Selection Input / Output data...

  • Page 49: R3 And R3Io Register

    MC80F0304/08/16 ADDRESS: 0C4 R2 Data Register RESET VALUE: 00 R27 R26 R25 R24 R23 R22 R21 Input / Output data ADDRESS: 0C5 R2 Direction Register RESET VALUE: 00 R2IO Port Direction 0: Input 1: Output R2 Pull-up ADDRESS: 0FE Selection Register...
  • Page 50 MC80F0304/08/16 ADDRESS: 0C6 R3 Data Register RESET VALUE: 00 R35 R34 R33 R32 R31 R30 Input / Output data Input data ADDRESS: 0C7 R3 Direction Register RESET VALUE: 00 R3IO Port Direction 0: Input 1: Output R3 Pull-up ADDRESS: 0FD...

  • Page 51: Clock Generator

    MC80F0304/08/16 10. CLOCK GENERATOR As shown in Figure 10-1 , the clock generator produces the basic through a divide-by-two flip-flop, but minimum and maximum clock pulses which provide the system clock to be supplied to the high and low times specified on the data sheet must be observed.
  • Page 52 Figure 10-4 External Clock Connections In addition to external crystal/resonator and external RC/R oscil- In addition, the MC80F0304/0308/0316 has an ability for the ex- lation, the MC80F0304/0308/0316 provides the internal 4MHz or 2MHz oscillation. The internal 4MHz/2MHz oscillation needs no ternal RC oscillated operation.

  • Page 53: Basic Interval Timer

    MC80F0304/08/16 11. BASIC INTERVAL TIMER The MC80F0304/0308/0316 has one 8-bit Basic Interval Timer If the STOP instruction executed after writing "1" to bit RCWDT that is free-run and can not stop. Block diagram is shown in Fig- of CKCTLR, it goes into the internal RC oscillated watchdog tim- ure 11-1 .
  • Page 54 MC80F0304/08/16 Interrupt (overflow) Period (ms) CKCTLR Source clock = 8MHz [2:0] ÷8 0.256 ÷16 0.512 ÷32 1.024 ÷64 2.048 ÷128 4.096 ÷256 8.192 16.384 ÷512 32.768 ÷1024 Table 11-1 Basic Interval Timer Interrupt Period ADDRESS: 0F2 CKCTLR BTCL BTS2 BTS1...
  • Page 55 MC80F0304/08/16 12. WATCHDOG TIMER The watchdog timer rapidly detects the CPU malfunction such as RCWDT as shown below. endless looping caused by noise or the like, and resumes the CPU to the normal state. The watchdog timer signal for detecting mal- CKCTLR,#3FH;...

  • Page 56: Watchdog Timer

    MC80F0304/08/16 time, selecting of output, and clearing of the binary counter. low to reset the internal hardware. When WDTON=0, a watchdog Clearing the binary counter is repeated within the detection time. timer interrupt (WDTIF) is generated. The WDTON bit is in reg- ister CLKCTLR.
  • Page 57 MC80F0304/08/16 Source clock BIT overflow Binary-counter Counter Counter Clear Clear WDTR Match Detect WDTIF interrupt WDTR ← “1000_0011 ” WDT reset reset Figure 12-3 Watchdog timer Timing If the watchdog timer output becomes active, a reset is generated, set is generated in sub clock mode.

  • Page 58: Timer/Event Counter

    MC80F0304/08/16 13. TIMER/EVENT COUNTER The MC80F0304/0308/0316 has Four Timer/Counter registers. Each module can generate an interrupt to indicate that an event counter function. When external clock edge input, the count reg- ister is captured into Timer data register correspondingly. When has occurred (i.e.
  • Page 59 MC80F0304/08/16 ADDRESS: 0D0 CAP0 T0CK2 T0CK1 BTCL T0CK0 T0CN T0ST INITIAL VALUE: --00 0000 Bit Name Bit Position Description CAP0 TM0.5 0: Timer/Counter mode 1: Capture mode selection flag T0CK2 TM0.4 000: 8-bit Timer, Clock source is f ÷ T0CK1 TM0.3...
  • Page 60 MC80F0304/08/16 ADDRESS: 0D6 CAP2 T2CK2 T2CK1 BTCL T2CK0 T2CN T2ST INITIAL VALUE: --00 0000 Bit Name Bit Position Description CAP2 TM2.5 0: Timer/Counter mode 1: Capture mode selection flag T2CK2 TM2.4 000: 8-bit Timer, Clock source is f ÷ T2CK1 TM2.3...

  • Page 61: 8-Bit Timer / Counter Mode

    MC80F0304/08/16 13.1 8-bit Timer / Counter Mode The MC80F0304/0308/0316 has four 8-bit Timer/Counters, Tim- PWM3E of TM1 or TM3 should be cleared to "0" (Figure 13-3 ). er 0, Timer 1, Timer 2, Timer 3. The Timer 0, Timer 1 are shown These timers have each 8-bit count register and data register.
  • Page 62 MC80F0304/08/16 ADDRESS: 0D6 CAP2 T2CK2 T2CK1 BTCL T2CK0 T2CN T2ST INITIAL VALUE: --000000 X means don’t care ADDRESS: 0D8 16BIT CAP3 T3CK1 BTCL T3CK0 T3CN T3ST PWM3E INITIAL VALUE: 00 X means don’t care T2CK[2:0] EDGE DETECTOR EC1 PIN T2ST ÷...
  • Page 63 MC80F0304/08/16 Example 1: These timers have each 8-bit count register and data register. The count register is increased by every internal or external clock in- Timer0 = 2ms 8-bit timer mode at 4MHz put. The internal clock has a prescaler divide ratio option of 2, 4, Timer1 = 0.5ms 8-bit timer mode at 4MHz...
  • Page 64 MC80F0304/08/16 Example: Make 1ms interrupt using by Timer0 at 4MHz TM0,#0FH ; divide by 32 TDR0,#124 ; 8us x (124+1)= 1ms SET1 ; Enable Timer 0 Interrupt ; Enable Master Interrupt When TM0 = 0000 1111 (8-bit Timer mode, Prescaler divide ratio = 32)

  • Page 65: 16-Bit Timer / Counter Mode

    MC80F0304/08/16 TDR1 enable disable clear & start stop TIME Timer 1 (T1IF) Interrupt Occur interrupt Occur interrupt Start & Stop T1ST T1ST = 1 T1CN T1ST = 0 Control count T1CN = 0 T1CN = 1 Figure 13-8 Count Operation of Timer / Event counter 13.2 16-bit Timer / Counter Mode...
  • Page 66 MC80F0304/08/16 ADDRESS: 0D0 CAP0 T0CK2 T0CK1 BTCL T0CK0 T0CN T0ST INITIAL VALUE: --00 0000 X means don’t care ADDRESS: 0D2 16BIT CAP1 T1CK1 BTCL T1CK0 T1CN T1ST PWM1E INITIAL VALUE: 00 X means don’t care T0CK[2:0] EDGE DETECTOR EC0 PIN T0ST ÷...

  • Page 67: 8-Bit Compare Output (16-Bit)

    Figure 13-10 16-bit Timer/Counter for Timer 2, 3 13.3 8-bit Compare Output (16-bit) The MC80F0304/0308/0316 has Timer Compare Output func- tion. To pulse out, the timer match can goes to port pin( T0O or nal having a 50 : 50 duty square wave, and output frequency is same as below equation.
  • Page 68 MC80F0304/08/16 of Timer. ter captured, Timer x register is cleared and restarts by hardware. For example, in Figure 13-14 , the pulse width of captured signal It has three transition modes: "falling edge", "rising edge", "both is wider than the timer data value (FF ) over 2 times.
  • Page 69 MC80F0304/08/16 ADDRESS: 0D0 CAP0 T0CK2 BTCL T0CK1 T0CK0 T0CN T0ST INITIAL VALUE: --00 0000 X means don’t care ADDRESS: 0D2 16BIT CAP1 BTCL T1CK1 T1CK0 T1CN T1ST PWM1E INITIAL VALUE: 00 X means don’t care T0CK[2:0] Edge Detector EC0 PIN T0ST ÷...
  • Page 70 MC80F0304/08/16 ADDRESS: 0D6 CAP2 T2CK2 BTCL T2CK1 T2CK0 T2CN T2ST INITIAL VALUE: --00 0000 X means don’t care ADDRESS: 0D8 16BIT CAP3 BTCL T3CK1 T3CK0 T3CN T3ST PWM3E INITIAL VALUE: 00 X means don’t care T2CK[2:0] Edge Detector EC1 PIN T2ST ÷...
  • Page 71 MC80F0304/08/16 This value is loaded to CDR0 TIME Ext. INT0 Pin Interrupt Request ( INT0IF ) Interrupt Interval Period Ext. INT0 Pin Interrupt Request ( INT0IF ) 20nS Delay Clear & Start Capture ( Timer Stop ) Figure 13-13 Input Capture Operation of Timer 0 Capture mode Ext.

  • Page 72: 16-Bit Capture Mode

    MC80F0304/08/16 13.5 16-bit Capture Mode 16-bit capture mode is the same as 8-bit capture, except that the Timer register is being run will 16 bits. The clock source of the The clock source of the Timer 2 is selected either internal or ex- ternal clock by bit T2CK[2:0].
  • Page 73 MC80F0304/08/16 ADDRESS: 0D6 CAP2 T2CK2 T2CK1 BTCL T2CK0 T2CN T2ST INITIAL VALUE: --00 0000 X means don’t care ADDRESS: 0D8 16BIT CAP3 T3CK1 BTCL T3CK0 T3CN T3ST PWM3E INITIAL VALUE: 00 X means don’t care T2CK[2:0] Edge Detector EC1 PIN T2ST ÷...

  • Page 74: Pwm Mode

    MC80F0304/08/16 13.6 PWM Mode The MC80F0304/0308/0316 has high speed PWM (Pulse Width Modulation) functions which shared with Timer1 or Timer3. resolution. In PWM mode, R10 / PWM1O or R11 / PWM3O pin output up Frequency to a 10-bit resolution PWM output. These pins should be config-...
  • Page 75 MC80F0304/08/16 ADDRESS: 0D2 16BIT CAP3 T1CK1 BTCL T1CK0 T1CN T1ST PWM1E INITIAL VALUE: 00 X:The value "0" or "1" corresponding your operation. ADDRESS: 0D5 T1PWHR BTCL T1PWHR3 T1PWHR2 T1PWHR1 T1PWHR0 INITIAL VALUE: ---- 0000 Bit Manipulation Not Available X:The value "0" or "1" corresponding your operation.
  • Page 76 MC80F0304/08/16 ADDRESS: 0D8 16BIT CAP3 T3CK1 BTCL T3CK0 T3CN T3ST PWM3E INITIAL VALUE: 00 X:The value "0" or "1" corresponding your operation. ADDRESS: 0DB T3PWHR BTCL T3PWHR3 T3PWHR2 T3PWHR1 T3PWHR0 INITIAL VALUE: ---- 0000 Bit Manipulation Not Available X:The value "0" or "1" corresponding your operation.
  • Page 77 MC80F0304/08/16 Source clock PWM1E T1ST T1CN PWM1O [POL=1] PWM1O [POL=0] Duty Cycle [ (1+7Fh) x 250nS = 32uS ] Period Cycle [ (3FFh+1) x 250nS = 256uS, 3.9KHz ] T1CK[1:0] = 00 ( XIN ) T1PPR (8-bit) Period T1PWHR3 T1PWHR2...

  • Page 78: Analog To Digital Converter

    MC80F0304/08/16 14. ANALOG TO DIGITAL CONVERTER The analog-to-digital converter (A/D) allows conversion of an analog input signal to a corresponding 10-bit digital value. The A/ set to “1”. After one cycle, it is cleared by hardware. The register ADCRH and ADCRL contains the results of the A/D conversion.
  • Page 79 MC80F0304/08/16 may not be obtainable due to coupling noise. Therefore, avoid ap- pedance of the analog power source is high, this will result in plying pulses to pins adjacent to the pin undergoing A/D conver- parallel connection to the series resistor string between the sion.
  • Page 80 MC80F0304/08/16 ADDRESS: 0EF ADCM BTCL ADEN ADCK ADS3 ADS2 ADS1 ADS0 ADST ADSF INITIAL VALUE: 0000 0001 A/D status bit 0: A/D conversion is in progress 1: A/D conversion is completed A/D start bit Setting this bit starts an A/D conversion.

  • Page 81: Serial Input/Output (Sio)

    MC80F0304/08/16 15. SERIAL INPUT/OUTPUT (SIO) The serial Input/Output is used to transmit/receive 8-bit data se- control circuit as illustrated in Figure 15-1 . The SO pin is de- rially. The Serial Input/Output (SIO) module is a serial interface signed to input and output. So the Serial I/O(SIO) can be operated useful for communicating with other peripheral of microcontrol- with minimum two pin.

  • Page 82: Transmission/Receiving Timing

    MC80F0304/08/16 Serial I/O Mode Register (SIOM) controls serial I/O function. Serial I/O Data Register (SIOR) is an 8-bit shift register. First According to SCK1 and SCK0, the internal clock or external LSB is send or is received first. clock can be selected.

  • Page 83: The Usage Of Serial I/O

    MC80F0304/08/16 SIOST SCK [R00] (POL=0) SO [R02] SI [R01] (IOSW=0) IOSWIN [R02] (IOSW=1) SIOIF (SIO Int. Req) SIOSF (SIO Status) Figure 15-3 Serial I/O Timing Diagram at POL=0 SIOST SCK [R00] (POL=1) SO [R02] SI [R01] (IOSW=0) IOSWIN [R02] (IOSW=1) SIOIF (SIO Int.
  • Page 84 MC80F0304/08/16 3. Set SIOST to “1” to start serial transmission. SIOR,#0AAh ;set tx data 4. The SIO interrupt is generated at the completion of SIO SIOM,#0011_1100b;set SIO mode and SIOIF is set to “1”. SIOM,#0011_1110b;SIO Start 5. In case of receiving mode, the received data is acquired SIO_WAIT: by reading the SIOR.

  • Page 85: Universal Asynchronous Receiver/ Transmitter (Uart)

    MC80F0304/08/16 16. UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART) 16.1 UART Serial Interface Functions The Universal Asynchronous Receiver / Transmitter (UART) en- ables full-duplex operation wherein one byte of data after the start The UART driver consists of RXR, TXR, ASIMR, ASISR and BRGCR register.

  • Page 86: Serial Interface Configuration

    MC80F0304/08/16 RECEIVE ACLK PIN 5-bit counter ÷2 ~ f ÷128 match (Divider) ÷2 Tx_Clock Decoder match ÷2 TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0 (Divider) Rx_Clock (BRGCR) 5-bit counter Internal Data Bus SEND Figure 16-2 Baud Rate Generator Block Diagram 16.2 Serial Interface Configuration...
  • Page 87 MC80F0304/08/16 ADDRESS: 0E6 ASIMR BTCL ISRM INITIAL VALUE: 0000 -00- UART Receive interrupt request is issued when an error occurs bit 0: Receive Completion Interrupt Control When Error occurs 1: Receive completion interrupt request is not issued when an error occur...
  • Page 88 MC80F0304/08/16 Asynchronous serial interface status register (ASISR) When a receive error occurs during UART mode, this register in- manipulation instruction. The RESET input sets ASISR to ----_- dicates the type of error. ASISR can be read by an 8 bit memory 000B.

  • Page 89: Communication Operation

    MC80F0304/08/16 Baud rate generator control register (BRGCR) This register sets the serial clock for serial interface. BRGCR is Figure 16-5 shows the format of BRGCR. set by an 8 bit memory manipulation instruction. The RESET in- put sets BRGCR to -001_0000B.

  • Page 90: Relationship Between Main Clock And Baud Rate

    MC80F0304/08/16 rupt request. 1. Stop bit Length : 1 bit 1 data frame Start Parity Stop character bits INTERRUPT INTERRUPT 2. Stop bit Length : 2 bit 1 data frame Start Parity Stop character bits INTERRUPT INTERRUPT 3. Stop bit Length : 1 bit, No parity...
  • Page 91 MC80F0304/08/16 system clock is determined according to the following formula. =11.05 =10.0M =8.0M =4.0M =2.0M Baud Rate (bps) BRGCR ERR(%) BRGCR ERR(%) BRGCR ERR(%) BRGCR BRGCR ERR(%) 0.16 0.16 1200 0.16 0.16 0.16 2400 0.00 1.73 0.16 0.16 0.16 4800 0.00...

  • Page 92: Buzzer Function

    MC80F0304/08/16 17. BUZZER FUNCTION The buzzer driver block consists of 6-bit binary counter, buzzer driving. register BUZR, and clock source selector. It generates square- wave which has very wide range frequency (488Hz ~ 250kHz at Equation of frequency calculation is shown below.
  • Page 93 MC80F0304/08/16 The 6-bit counter is cleared and starts the counting by writing sig- When main-frequency is 4MHz, buzzer frequency is shown as nal at BUZR register. It is incremental from 00 until it matches below Table 17-1. 6-bit BUR value.

  • Page 94: Interrupts

    MC80F0304/08/16 18. INTERRUPTS The MC80F0304/0308/0316 interrupt circuits consist of Interrupt enable register (IENH, IENL), Interrupt request flags of IRQH, The Timer 0 ~ Timer 3 Interrupts are generated by T0IF, T1IF, T2IF and T3IF which is set by a match in their respective timer/ IRQL, Priority circuit, and Master enable flag (“I”...
  • Page 95 MC80F0304/08/16 The UART receive or transmit interrupts are generated by UAR- TRIF or UARTTIF are set by completion of UART data recep- tion or transmission. Reset/Interrupt Symbol Priority The SIO interrupt is generated by SIOIF which is set by comple- tion of SIO data reception or transmission.

  • Page 96: Interrupt Sequence

    MC80F0304/08/16 ADDRESS: 0EC IRQH T0IF INT0IF INT1IF INT2IF INT3IF SIOIF UARTRIF UARTTIF INITIAL VALUE: 0000 0000 Timer/Counter 0 interrupt request flag Serial Communication interrupt request flag UART Tx interrupt request flag UART Rx interrupt request flag External interrupt 3 request flag...
  • Page 97 MC80F0304/08/16 rupt service program is executed. System clock Instruction Fetch SP-2 V.L. V.H. New PC SP-1 Address Bus Not used Data Bus V.L. OP code Internal Read Internal Write Interrupt Processing Step Interrupt Service Task V.L. and V.H. are vector addresses.

  • Page 98: Brk Interrupt

    MC80F0304/08/16 Example: Register save using push and pop instructions ;RESTORE Y REG. ;RESTORE X REG. INTxx: CLR1 INTxxIF ;CLEAR REQUEST. ;RESTORE ACC. PUSH PUSH ;SAVE ACC. ;SAVE X REG. RETI ;RETURN PUSH ;SAVE Y REG. General-purpose register save/restore using push and pop instruc- interrupt processing tions;...

  • Page 99: External Interrupt

    MC80F0304/08/16 interrupt can be serviced even if certain interrupt is in progress. Main Program service TIMER 1 service enable INT0 INT0 service disable other Occur Occur In this example, the INT0 interrupt can be serviced without any TIMER1 interrupt INT0 pending, even TIMER1 is in progress.
  • Page 100 MC80F0304/08/16 INT0 pin INT0IF INT0 INTERRUPT INT1 pin INT1IF INT1 INTERRUPT INT2 pin INT2IF INT2 INTERRUPT INT3 pin INT3IF INT3 INTERRUPT IEDS Edge selection Register [0EEH] Figure 18-7 External Interrupt Block Diagram INT0 ~ INT3 are multiplexed with general I/O ports (R11, R12, R03, R00).
  • Page 101 MC80F0304/08/16 ADDRESS: 0EE IEDS IED3H IED3L IED2H IED2L IED1H BTCL IED1L IED0H IED0L INITIAL VALUE: 00 INT3 INT2 INT1 INT0 Edge selection register 00: Reserved 01: Falling (1-to-0 transition) 10: Rising (0-to-1 transition) 11: Both (Rising & Falling) ADDRESS: 0F8...

  • Page 102: Power Saving Operation

    MC80F0304/08/16 19. POWER SAVING OPERATION The MC80F0304/0308/0316 has two power-down modes. In power-down mode, power consumption is reduced considerably. and SLEEP mode. Table 19-1 shows the status of each Power Saving Mode. SLEEP mode is entered by the SSCR register to For applications where power consumption is a critical factor, de- “0Fh”., and STOP mode is entered by STOP instruction after the...

  • Page 103: Stop Mode

    MC80F0304/08/16 Oscillator pin) Internal Clock External Interrupt SLEEP Instruction Executed Normal Operation SLEEP Operation Normal Operation Figure 19-2 SLEEP Mode Release Timing by External Interrupt Oscillator pin) Clock RESET Internal RESET SLEEP Instruction Stabilization Time Execution = 65.5mS @4MHz Normal Operation...
  • Page 104 MC80F0304/08/16 ing on the external circuitry and program) is not directly deter- Note: After STOP instruction, at least two or more NOP instruc- mined by the hardware operation of the STOP feature. This point tion should be written. LDM CKCTLR,#0FH ;more than 20ms...
  • Page 105 MC80F0304/08/16 STOP INSTRUCTION STOP Mode Interrupt Request Corresponding Interrupt IENH or IENL ? Enable Bit (IENH, IENL) STOP Mode Release Master Interrupt I-FLAG Enable Bit PSW[2] Interrupt Service Routine Next INSTRUCTION Figure 19-4 STOP Releasing Flow by Interrupts Oscillator pin)

  • Page 106: Stop Mode At Internal Rc-Oscillated Watchdog Timer Mode

    MC80F0304/08/16 STOP Mode Oscillator (XI pin) Internal Clock RESET Internal RESET STOP Instruction Execution Stabilization Time Time can not be control by software = 65.5mS @4MHz Figure 19-6 Timing of STOP Mode Release by Reset 19.3 Stop Mode at Internal RC-Oscillated Watchdog Timer Mode In the Internal RC-Oscillated Watchdog Timer mode, the on-chip (at RC-watchdog timer mode).

  • Page 107: Minimizing Current Consumption

    MC80F0304/08/16 Oscillator pin) Internal RC Clock Internal Clock External Interrupt ( or WDT Interrupt ) Clear Basic Interval Timer STOP Instruction Execution Counter Normal Operation Stabilization Time STOP mode Normal Operation at RC-WDT Mode > 20mS Figure 19-7 Stop Mode Release at Internal RC-WDT Mode by External Interrupt or WDT Interrupt...
  • Page 108 MC80F0304/08/16 tical. INPUT PIN INPUT PIN internal pull-up OPEN Very weak current flows OPEN Weak pull-up current flows When port is configured as an input, input level should be closed to 0V or 5V to avoid power consumption. Figure 19-9 Application Example of Unused Input Port...
  • Page 109 MC80F0304/08/16 High or Low is decided by considering its relationship with exter- down register, it is set to low. nal circuit. For example, if there is external pull-up resistor then it is set to output mode, i.e. to High, and if there is external pull-...
  • Page 110 MC80F0304/08/16 20. RESET The MC80F0304/0308/0316 supports various kinds of reset as below. • Watchdog Timer Timeout Reset • Power-Fail Detection (PFD) Reset • Power-On Reset (POR) • Address Fail Reset • RESET (external reset circuitry) RESET Noise Canceller (Power-On Reset)
  • Page 111 MC80F0304/08/16 Oscillator pin) RESET ADDRESS FFFE FFFF Start DATA MAIN PROGRAM Stabilization Time =65.5mS at 4MHz Reset Process Step x 256 ÷1024 Figure 20-3 Timing Diagram after Reset The Address Fail Reset is the function to reset the system by code area or RAM area, the address fail reset is occurred.

  • Page 112: Power Fail Processor

    MC80F0304/08/16 21. POWER FAIL PROCESSOR The MC80F0304/0308/0316 has an on-chip power fail detection circuitry to immunize against power noise. A configuration reg- age Detector Register” on page 112. ister, PFDR, can enable or disable the power fail detect circuitry. In the in-circuit emulator, power fail function is not implemented...
  • Page 113 MC80F0304/08/16 65.5mS Internal RESET When PFDM = 1 65.5mS Internal t < 65.5mS RESET 65.5mS Internal RESET Figure 21-3 Power Fail Processor Situations (at 4MHz operation) November 4, 2011 Ver 2.12...

  • Page 114: Countermeasure Of Noise

    “ONP” bit of the Device - Change system clock to the internal oscillation clock configuration area (20FF ) for the MC80F0304/0308/0316, when the X is shorted or opened, the main “ONP” option bits MASK option.

  • Page 115: Oscillation Fail Processor

    22.2 Oscillation Fail Processor The oscillation fail processor (OFP) can change the clock source Configuration Area (MASK option for MC80F0304/0308/0316) from external to internal oscillator when the oscillation fail oc- enables the function to operate the device by using the internal os- cured.

  • Page 116: Device Configuration Area

    MC80F0304/08/16 DEVICE CONFIGURATION AREA The Device Configuration Area can be programmed or left un- Note: The Configuration Option may not be read exactly programmed to select device configuration such as POR, ONP, when VDD rising time is very slow. It is recommended to CLK option and security bit.

  • Page 117: Mask Option (Mc80C0304/08/16)

    MC80F0304/08/16 24. MASK OPTION (MC80C0304/08/16) The MC80C0304/08/16 has several MASK option which config- checked to select device configuration such as package type, Os- ures the package type or use of some special features of the de- cillation selection, oscillation noise protector, oscillation fail pro- vice.

  • Page 118: Emulator Eva. Board Setting

    MC80F0304/08/16 25. EMULATOR EVA. BOARD SETTING À Œ œ – — Ã Õ þ November 4, 2011 Ver 2.12...

  • Page 119: Dip Switch And Vr Setting

    MC80F0304/08/16 25.1 DIP Switch and VR Setting Before execute the user program, keep in your mind the below configuration DIP S/W Description ON/OFF Setting þ This connector is only used for a device over 32 PIN. For the MC80F0224/MC80F0448 À...
  • Page 120 MC80F0304/08/16 DIP S/W Description ON/OFF Setting — Must be OFF position. ON : For the MC80F0224/MC80F0448. OFF : For the MC80F0316. Eva. select switch November 4, 2011 Ver 2.12...

  • Page 121: In-System Programming (Isp)

    MC80F0304/08/16 26. IN-SYSTEM PROGRAMMING (ISP) 26.1 Getting Started / Installation The following section details the procedure for accomplishing the 3. Turn your target B/D power switch ON. Your target B/ installation procedure. D must be configured to enter the ISP mode.

  • Page 122: Hardware Conditions To Enter The Isp Mode

    MC80F0304/08/16 Function Description Load HEX File Load the data from the selected file storage into the memory buffer. Save HEX File Save the current data in your memory buffer to a disk storage by using the Intel Motorolla HEX format.
  • Page 123 MC80F0304/08/16 5) Select target MCU - It makes condition to make Vpp to neously. turn on when Vdd is turned on. 6) Power on a target system. : At this point, ISP mode is en- tered because the Vdd and Vpp are turned on simulta-...

  • Page 124: Sequence To Enter Isp Mode/User Mode

    Note: Need to connect the ACK pin to ISP B/D. 26.6 Reference ISP Circuit Diagram and ABOV Supplied ISP Board The ISP software and hardware circuit diagram are provided at www.abov.co.kr . To get a ISP B/D, contact to sales department. November 4, 2011 Ver 2.12...
  • Page 125 V For the ISP operation, power consumption required is minimum 30mA. Figure 26-2 Reference ISP Circuit Diagram Figure 26-3 ISP board supplied by ABOV November 4, 2011 Ver 2.12...
  • Page 126 MC80F0304/08/16 November 4, 2011 Ver 2.12...
  • Page 127 MC80F0304/08/16 APPENDIX November 4, 2011 Ver 2.12...

  • Page 128: Instruction

    MC80F0304/08/16 A. INSTRUCTION A.1 Terminology List Terminology Description Accumulator X - register Y - register Program Status Word #imm 8-bit Immediate data Direct Page Offset Address !abs Absolute Address Indirect expression Register Indirect expression { }+ Register Indirect expression, after that, Register auto-increment .bit...

  • Page 129: Instruction Map

    MC80F0304/08/16 A.2 Instruction Map 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 HIGH SET1 TCALL SETA1 PUSH dp.bit A.bit,rel dp.bit,rel #imm dp+X !abs .bit TCALL CLRA1 PUSH CLRC “ “ “ #imm...

  • Page 130: Instruction Set

    MC80F0304/08/16 A.3 Instruction Set Arithmetic / Logic Operation BYTE CYCLE FLAG MNEMONIC OPERATION NVGBHIZC CODE ADC #imm ADC dp ADC dp + X ADC !abs Add with carry. NV--H-ZC A ← ( A ) + ( M ) + C...
  • Page 131 MC80F0304/08/16 BYTE CYCLE FLAG MNEMONIC OPERATION CODE NVGBHIZC EOR #imm EOR dp EOR dp + X EOR !abs Exclusive OR N-----Z- EOR !abs + Y A ← ( A ) ⊕ ( M ) EOR [ dp + X ]...
  • Page 132 MC80F0304/08/16 Register / Memory Operation BYTE CYCLE FLAG MNEMONIC OPERATION CODE NVGBHIZC LDA #imm LDA dp LDA dp + X LDA !abs Load accumulator LDA !abs + Y A ← ( M ) N-----Z- LDA [ dp + X ]...
  • Page 133 MC80F0304/08/16 16-BIT Operation BYTE CYCLE FLAG MNEMONIC OPERATION NVGBHIZC CODE 16-Bits add without carry ADDW dp NV--H-ZC YA ← ( YA ) + ( dp +1 ) ( dp ) (YA) − Compare YA contents with memory pair contents :...
  • Page 134 MC80F0304/08/16 Branch / Jump Operation BYTE CYCLE FLAG MNEMONIC OPERATION CODE NVGBHIZC BBC A.bit,rel Branch if bit clear : -------- if ( bit ) = 0 , then pc ← ( pc ) + rel BBC dp.bit,rel BBS A.bit,rel Branch if bit set : -------- if ( bit ) = 1 , then pc ←...
  • Page 135 MC80F0304/08/16 Control Operation & Etc. BYTE CYCLE FLAG MNEMONIC OPERATION CODE NVGBHIZC Software interrupt : B ← ”1”, M(sp) ← (pc ), sp ←sp-1, M(s) ← (pc ), sp ← sp - 1, M(sp) ← (PSW), sp ← sp -1, ---1-0-- ←...
  • Page 136 “00H” EFFF F000 .OTP file data (Please check mark into FFFF 4. Delivery Schedule Quantity Date ABOV Confirmation YYYY Customer Sample Risk Order 5. ROM Code Verification Fax: Verification Date: Tel: Name & Check Sum:...
  • Page 137 “00H” EFFF F000 .OTP file data (Please check mark into FFFF 4. Delivery Schedule Quantity Date ABOV Confirmation YYYY Customer Sample Risk Order 5. ROM Code Verification Fax: Verification Date: Tel: Name & Check Sum:...
  • Page 138 “00H” EFFF F000 .OTP file data (Please check mark into FFFF 4. Delivery Schedule Quantity Date ABOV Confirmation YYYY Customer Sample Risk Order 5. ROM Code Verification Fax: Verification Date: Tel: Name & Check Sum:...

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