Transmission/Receiving Timing - Abov MC80F0304 User Manual

MC80F0304/08/16
Serial I/O Mode Register (SIOM) controls serial I/O function. Serial I/O Data Register (SIOR) is an 8-bit shift register. First
According to SCK1 and SCK0, the internal clock or external LSB is send or is received first.
clock can be selected.
R/W R/W R/W R/W R/W R/W R/W R
SIOM 7 6 5 4 3 2 1 0 ADDRESS: 0E2 H
POL IOSW SM1 SM0 SCK1 SCK0 BTCL SIOST SIOSF INITIAL VALUE: 0000 0001 B
Serial transmission status bit
1: Serial transmission is completed 0: Serial transmission is in progress
Serial transmission start bit Setting this bit starts an Serial transmission.
After one cycle, bit is cleared to "0" by hardware.
Serial transmission Clock selection ÷ 4
00: f 01: f XIN XIN ÷ 16
10: TMR0OV(Timer0 Overflow) 11: External Clock
00: Normal Port(R00,R01,R02) Serial transmission Operation Mode
01: Sending Mode(SCK,R01,SO) 10: Receiving Mode(SCK,SI,R02)
11: Sending & Receiving Mode(SCK,SI,SO)
Serial Input Pin Selection bit
0: SI Pin Selection 1: SO Pin Selection
0: Data Transmission at Falling Edge Serial Clock Polarity Selection bit
Received Data Latch at Rising Edge
1: Data Transmission at Rising Edge Received Data Latch at Falling Edge
R/W 7 6 R/W R/W R/W R/W 5 4 3 2 R/W 1 R/W R/W 0
SIOR BTCL ADDRESS: 0E3 INITIAL VALUE: Undefined H
Sending Data at Sending Mode
Receiving Data at Receiving Mode
Figure 15-2 SIO Control Register

15.1 Transmission/Receiving Timing

to "1". After one cycle of SCK, SIOST and SIOSF(bit 0 of SIOM) The serial transmission is started by setting SIOST(bit1 of SIOM) counted 8 times, serial I/O counter is cleared as '0". Transmission SCLK pin (Refer to Figure 15-3 ). When transmission clock is
is cleared automatically to "0". At the default state of POL bit clock is halted in "H" state and serial I/O interrupt (SIOIF) oc-
clear, the serial output data from 8-bit shift register is output at curred. SIOSF is set to "1" automatically.
falling edge of SCLK, and input data is latched at rising edge of
82 November 4, 2011 Ver 2.12