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Abov MC95FG0128A User Manual

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MC95FG0128A
ABOV SEMICONDUCTOR Co., Ltd.
8-BIT MICROCONTROLLERS
MC95FG0128A
User's Manual
(Ver. 2.9)
Aug 02, 2018 Ver.2.9
1

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  • Page 1 MC95FG0128A ABOV SEMICONDUCTOR Co., Ltd. 8-BIT MICROCONTROLLERS MC95FG0128A User’s Manual (Ver. 2.9) Aug 02, 2018 Ver.2.9...

  • Page 2: Revision History

    MC95FG0128A REVISION HISTORY VERSION COMMENT DATE Modified Internal RC oscillator spec. (Chapter 7.7, 7.8) (Aug 02, 2018) Update Development Tools. (Chapter 1.4) Add Device Nomenclature. Add “direct input port Bit test and branch” instruction warning (April 30, 2015) Change Configure Option naming.
  • Page 3 The information, diagrams and other data in this manual are correct and reliable. However, ABOV Semiconductor is in no way responsible for any violations of patents or other rights of the third party generated by the use of this manual.

  • Page 4: Table Of Contents

    MC95FG0128A Table of Contents REVISION HISTORY ............................2 Table of Contents..............................4 List of Figures ................................. 7 MC95FG0128A ..............................10 1. Overview ................................10 1.1 Description ..............................10 1.2 Features ..............................10 1.3 Ordering Information ..........................12 1.4 Development Tools ............................ 13 2.
  • Page 5 MC95FG0128A 10.5 Interrupt Sequence ........................... 62 10.6 Effective Timing after Controlling Interrupt bit ..................64 10.7 Multi Interrupt ............................65 10.8 Interrupt Enable Accept Timing ......................66 10.9 Interrupt Service Routine Address ......................66 10.10 Saving/Restore General-Purpose Registers .................... 66 10.11 Interrupt Timing .............................
  • Page 6 MC95FG0128A 16. Configure option ............................196 16.1 Configure option Control Register ......................196 17. APPENDIX ..............................197 Aug 02, 2018 Ver.2.9...

  • Page 7: List Of Figures

    Figure 2.2 MC95FG8128A block diagram ................... 19 Figure 2.3 MC95FG6128A block diagram ................... 20 Figure 3.1 MC95FG0128A 100 Pin LQFP assignment ................ 21 Figure 3.2 MC95FG0128A 80 Pin LQFP assignment ................22 Figure 4.1 100 pin LQFP package ......................26 Figure 4.2 80 pin LQFP package ......................
  • Page 8 MC95FG0128A Figure 11.9 16 Bit Timer/Event Counter0, 1 Block Diagram ............... 89 Figure 11.10 8-bit Capture Mode for Timer0, 1 ................... 90 Figure 11.11 Input Capture Mode Operation of Timer 0, 1 ..............91 Figure 11.12 Express Timer Overflow in Capture Mode ..............91 Figure 11.13 16-bit Capture Mode of Timer 0, 1 ..................
  • Page 9 MC95FG0128A Figure 12.2 IDLE Mode Release Timing by /RESET ................ 160 Figure 12.3 STOP Mode Release Timing by External Interrupt ............161 Figure 12.4 STOP Mode Release Timing by /RESET ................ 161 Figure 12.5 STOP1, 2 Mode Release Flow ..................162 Figure 13.1 RESET Block Diagram ....................

  • Page 10: Mc95Fg0128A

    1. Overview 1.1 Description The MC95FG0128A is an advanced CMOS 8-bit microcontroller with 128K bytes of FLASH. This is powerful microcontroller which provides a highly flexible and cost effective solution to many embedded control applications. This provides the following features : 128K bytes of FLASH, 256...
  • Page 11 MC95FG0128A • Watch Dog Timer • On-Chip PLL • Watch Timer - 1.38MHz ~ 20.18MHz (with 32.768KHz) • Power On Reset • 2 SPI • 4 USART (4th usart can use only 100pin) - 1.4V • Programmable Brown-Out Detector • I - 1.6V / 2.5V / 3.6V / 4.2V...

  • Page 12: Ordering Information

    MC95FG0128A 1.3 Ordering Information Table 1-1 Ordering Information of MC95FG0128A Device name ROM size SRAM size XRAM size EEPROM size Package MC95FG0128AL 100 LQFP 80 LQFP MC95FG8128AL MC95FG8128AQ 80 MQFP 128 Kbytes FLASH 256 bytes 8 Kbytes 4 Kbytes MC95FG6128AL...

  • Page 13: Development Tools

    ABOV Semiconductor dose not provide compiler. It is recommended that you consult a compiler provider. The MC95FG0128A core is Mentor 8051. Device ROM size of standard 8051 is smaller than 64KB. Developer can use all kinds of third party’s standard 8051 compiler. But MC95FG0128A has 128KB code ROM area and uses memory banking scheme for this extended ROM.

  • Page 14: Figure 1.3 Ocd Interface Circuit

    MC95FG0128A E-PGM+, PGM Plus LC2, E-PGM+ Gang4/6 R1 (2k ~ 5k ) DSCL(I) To application circuit R2 (2k ~ 5k ) DSDA(I/O) To application circuit Figure 1.3 OCD Interface Circuit NOTE) In on-board programming mode, very high-speed signal will be provided to pin DSCL and DSDA.

  • Page 15: Figure 1.4 E-Pgm+ Component And Connector

    MC95FG0128A 1.4.3 Programmer E-PGM + • Support ABOV / ADAM devices • 2~5 times faster than S-PGM+ • Main controller : 32-bit MCU @ 72MHz • Buffer memory : 1MB Figure 1.4 E-PGM+ component and connector Aug 02, 2018 Ver.2.9...

  • Page 16: Figure 1.5 Pgmpluslc Writer

    MC95FG0128A PGMPlusLC 2 Description PGMPlusLC2 is for ISP (In System Programming). It is used to write into the MCU Which is already mounted on target board using 10pin cable. Features • PGMplusLC2 is low cost writing Tool. • USB interface is supported.

  • Page 17: Figure 1.6 E-Pgm+ Gang4/6 Programmer

    MC95FG0128A E-PGM+ Gang4/6 • Product name : E-PGM+ GANG 4 • Dimension(x , y, h) : 33.5 x 22.5 x35mm • Weight : 2.0kg • Input Voltage : DC Adaptor 15V/2A • Operating Temp : -10 ~ 40℃ • Storage Temp : -30 ~ 80℃...

  • Page 18: Block Diagram

    P30/USS1 P13/INT3 P43/RxD2 P14/INT4 P42/TxD2 P15/INT5 USART2 Voltage P41/ACK2 P16/INT6 Down P40/USS2 P17/INT7 Convertor P93/RxD3 P92/TxD3 USART3 SUBXIN/P04 P91/ACK3 (100pin only) P90/USS3 SUBXOUT/P05 CLOCK/ P07/SDA SYSTEM XIN/P62 P06/SCL XOUT/P63 nRESET VDD18 Figure 2.1 MC95FG0128A block diagram Aug 02, 2018 Ver.2.9...

  • Page 19: Figure 2.2 Mc95Fg8128A Block Diagram

    MC95FG0128A nTEST DSCL / DSDA P36/AN14 P35/AN13 P07~P00 PORT P34/AN12 P33/AN11 P17~P10 On –Chip PORT P32/AN10 Debug P31/AN9 12-BIT P27~P20 P30/AN8 PORT P27/AN7 P26/AN6 P37~P30 P25/AN5 PORT P24/AN4 M8051 P23/AN3 P47~P40 CORE PORT P22/AN2 P21/AN1 P57~P50 P20/AVREF/AN0 PORT P67~P60 P51/EC0...

  • Page 20: Figure 2.3 Mc95Fg6128A Block Diagram

    MC95FG0128A nTEST DSCL / DSDA P36/AN14 P35/AN13 P07~P00 PORT P34/AN12 P33/AN11 P17~P10 On –Chip PORT P32/AN10 Debug P31/AN9 12-BIT P27~P20 P30/AN8 PORT P27/AN7 P26/AN6 P37~P30 P25/AN5 PORT P24/AN4 M8051 P23/AN3 P47~P40 CORE PORT P22/AN2 P21/AN1 P57~P50 P20/AVREF/AN0 PORT P63~P60 P51/EC0...

  • Page 21: Pin Assignmnet

    P14/INT4 P36/MOSI0/AN14 P15/INT5 P35/SCK0/AN13 P34/SSS0/AN12 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Figure 3.1 MC95FG0128A 100 Pin LQFP assignment Aug 02, 2018 Ver.2.9...

  • Page 22: Figure 3.2 Mc95Fg0128A 80 Pin Lqfp Assignment

    P41/ACK2 P12/INT2 P40/USS2 P13/INT3 P37/MISO0 P14/INT4 P36/MOSI0/AN14 P15/INT5 P35/SCK0/AN13 P34/SSS0/AN12 38 39 40 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 Figure 3.2 MC95FG0128A 80 Pin LQFP assignment Aug 02, 2018 Ver.2.9...
  • Page 23 P41/ACK2 P13/INT3 P40/USS2 P37/MISO0 P14/INT4 P36/MOSI0/AN14 P15/INT5 P35/SCK0/AN13 P34/SSS0/AN12 P16/INT6 P33/RxD1/AN11 P17/INT7 P32/TxD1/AN10 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Figure 3-3 MC95FG0128A 80 Pin MQFP assignment Aug 02, 2018 Ver.2.9...
  • Page 24 P52/T0 P01/PCI01/ACK0 P51/EC0 P02/PCI02/TxD0 P50/BUZ P03/PCI03/RxD0 P47/MISO1 P04/PCI04/SUBXIN P46/MOSI1 P05/PCI05/SUBXOUT P45/SCK1 P06/PCI06/SCL P44/SSS1 P07/PCI07/SDA MC95FG6128AL P43/RxD2 P10/INT0 P42/TxD2 P11/INT1 P41/ACK2 P12/INT2 P40/USS2 P13/INT3 P37/MISO0 P14/INT4 P36/MOSI0/AN14 P15/INT5 P35/SCK0/AN13 P34/SSS0/AN12 Figure 3-4 MC95FG0128A 64 pin LQFP assignment Aug 02, 2018 Ver.2.9...
  • Page 25 P52/T0 P01/PCI01/ACK0 P51/EC0 P02/PCI02/TxD0 P50/BUZ P03/PCI03/RxD0 P47/MISO1 P04/PCI04/SUBXIN P46/MOSI1 P05/PCI05/SUBXOUT P45/SCK1 P06/PCI06/SCL P44/SSS1 MC95FG6128AL14 P07/PCI07/SDA P43/RxD2 P10/INT0 P42/TxD2 P11/INT1 P41/ACK2 P12/INT2 P40/USS2 P13/INT3 P37/MISO0 P14/INT4 P36/MOSI0/AN14 P15/INT5 P35/SCK0/AN13 P34/SSS0/AN12 Figure 3-5 MC95FG0128A 64 pin LQFP14 assignment Aug 02, 2018 Ver.2.9...

  • Page 26: Package Diagram

    MC95FG0128A 4. Package Diagram Figure 4.1 100 pin LQFP package Aug 02, 2018 Ver.2.9...

  • Page 27: Figure 4.2 80 Pin Lqfp Package

    MC95FG0128A Figure 4.2 80 pin LQFP package Aug 02, 2018 Ver.2.9...

  • Page 28: Figure 4.3 80 Pin Mqfp Package

    MC95FG0128A Figure 4.3 80 pin MQFP package Aug 02, 2018 Ver.2.9...

  • Page 29: Figure 4.4 64 Pin Lqfp Package

    MC95FG0128A Figure 4.4 64 pin LQFP package Aug 02, 2018 Ver.2.9...

  • Page 30: Figure 4.5 64 Pin Lqfp14 Package

    MC95FG0128A Figure 4.5 64 pin LQFP14 package Aug 02, 2018 Ver.2.9...

  • Page 31: Pin Description

    MC95FG0128A 5. Pin Description Table 5-1 Normal Pin description PIN Name Function @RESET Shared with Port P0 USS0/PCI0 8-Bit I/O Port ACK0/PCI0 Can be set in input or output mode in 1-bit TxD0/PCI0 units Internal pull-up register can be used via...
  • Page 32 MC95FG0128A AN8~AN14 can be selected by ADCM register AN14/MOSI0 MISO0 Port P4 USS2 8-Bit I/O Port ACK2 Can be set in input or output mode in 1-bit TxD2 units Internal pull-up register can be used via RxD2 software when this port is used as input port...
  • Page 33 MC95FG0128A Port P8 8-Bit I/O Port Can be set in input or output mode in 1-bit units Internal pull-up register can be used via Input software when this port is used as input port Open Drain enable register can be used via...
  • Page 34 MC95FG0128A SUBXIN Sub Oscillator input OCD Data input/output DSDA Input If it doesn’t use, it need pull-up resistor OCD clock input DSCL Input If it doesn’t use, it need pull-up resistor TEST mode enable nTEST is the same function like internal POR...

  • Page 35: Port Structures

    MC95FG0128A 6. Port Structures 6.1 General Purpose I/O Port LevelShift ( 1.8V to ExtVDD) LevelShift (ExtVDD to 1.8V) PULL-UP REGISTER OPEN DRAIN REGISTER DATA REGISTER SUB-FUNC DATA OUTPUT SUB-FUNC ENABLE DIRECTION REGISTER SUB-FUNC DIRECTION R(400Ω) PORTx INPUT CMOS or SchmittLevel...

  • Page 36: External Interrupt I/O Port

    MC95FG0128A 6.2 External Interrupt I/O Port LevelShift ( 1.8V to ExtVDD) LevelShift (ExtVDD to 1.8V) PULL-UP REGISTER OPEN DRAIN REGISTER DATA REGISTER SUB-FUNC DATA OUTPUT SUB-FUNC ENABLE DIRECTION REGISTER EXTERNAL SUB-FUNC DIRECTION INTERRUPT INTERRUPT ENABLE R(400Ω) EDGE POLARITY FLAG CLEAR...

  • Page 37: Electrical Characteristics

    MC95FG0128A 7. Electrical Characteristics 7.1 Absolute Maximum Ratings Table 7-1 Absolute Maximum Rationgs Parameter Symbol Rating Unit -0.3~+6.5 Supply Voltage -0.3~+0.3 -0.3~VDD+0.3 -0.3~VDD+0.3 Normal Voltage Pin ∑ ∑ Total Power Dissipation ℃ Storage Temperature TSTG -65~+150 Note) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.

  • Page 38: A/D Converter Characteristics

    MC95FG0128A 7.3 A/D Converter Characteristics Table 7-3 A/D Converter Characteristics (TA=-40℃ ~ +85℃, VDD=AVDD=2.7V ~ 5.5V, VSS=0V) Parameter Symbol Condition Unit Resolution bits Total Accuracy ± Integral Linear Error ±2 AVDD=VDD=5.12V Differential Linearity ±2 Error fXIN=4MHz Zero Offset Error ±...

  • Page 39: Power-On Reset Characteristics

    MC95FG0128A 7.5 Power-On Reset Characteristics Table 7-5 Power-On Reset Characteristics Parameter Symbol Condition Unit Operating Voltage ℃ Operating Temperature RESET Release Level Operating Current SIDD 7.6 Brown Out Detector Characteristics Table 7-6 Brown Out Detector Characteristics Parameter Symbol Condition Unit Operating Voltage ℃...

  • Page 40: Ring-Oscillator Characteristics

    MC95FG0128A 7.8 Ring-Oscillator Characteristics Table 7-8 Ring-Oscillator Characteristics Parameter Symbol Condition Unit Operating Voltage ℃ Operating Temperature Frequency Stabilization Time Operating Current SIDD 7.9 PLL Characteristics ( TA = 0℃ ~ +70℃, VDD18 = 1.6V ~ 2.0V, VSS = 0V )

  • Page 41: Dc Characteristics

    MC95FG0128A 7.10 DC Characteristics Table 7-10 DC Characteristics (VDD =2.7~5.5V, VSS =0V, fXIN=10.0MHz, TA=-40~+85℃) Parameter Symbol Condition Unit VIL1 nTEST, nRESET, DSCL, DSDA -0.5 0.2VDD VIL2 P0,P1,P2,P4,P5,P6,P7,P8,P9,PA -0.5 0.2VDD Input Low Voltage VIL3 P3 (VDD=4.0~5.5V) -0.5 0.1VDD+0.4 VIL4 P3 (VDD=2.7~4.0V) -0.5...

  • Page 42: Ac Characteristics

    MC95FG0128A 7.11 AC Characteristics (VDD=5.0V±10%, VSS=0V, TA=-40~+85℃) Table 7-11 AC Characteristics Parameter Symbol Unit Operating Frequency fMCP System Clock Cycle Time tSYS 1000 Oscillation Stabilization Time (8MHz) tMST1 XIN, XOUT External Clock “H” or “L” Pulse Width tCPW External Clock Transition Time...

  • Page 43: Spi Characteristics

    MC95FG0128A 7.12 SPI Characteristics (VDD=5.0V±10%, VSS=0V, TA=-40~+85℃) Table 7-12 SPI Characteristics Parameter Symbol Unit Output Clock Pulse Period tSCK clock mode Input Clock Pulse Period tSCK 2• tSYS Input Clock “H” or “L” Pulse Width tSCKL, tSCKH duty Input Clock Pulse Transition Time tFSCK,tRSCK Output Clock “H”...

  • Page 44: Typical Characteristics

    MC95FG0128A 7.13 Typical Characteristics These graphs and tables provided in this section are for design guidance only and are not tested or guaranteed. In some graphs or tables the data presented are outside specified operating range (e.g. outside specified VDD range). This is for information only and devices are guaranteed to operate properly only within the specified range.

  • Page 45: Memory

    Program memory can only be read, not written to. There can be up to 64K bytes of Program memory in a bank. In the MC95FG0128A FLASH version of these devices the 128K bytes of Program memory are provided on-chip. Data memory can be read and written to up to 256 bytes internal memory (DATA) including the stack area and 8K bytes of external data memory(XRAM).

  • Page 46: Figure 8.1 Program Memory

    MC95FG0128A FFFFH Total 128K Bytes 64K Bytes 64K Bytes Bank 1 0000H Bank 0 Figure 8.1 Program memory User Function Mode: 128KBytes Included Interrupt Vector Region Non-volatile and reprogramming memory: Flash memory based on EEPROM cell Aug 02, 2018 Ver.2.9...

  • Page 47: Data Memory

    MC95FG0128A 8.2 Data Memory Figure 8.2 shows the internal Data memory space available. Upper Special Function Registers 128 Bytes Internal RAM 128 Bytes (Direct Addressing) (Indirect Addressing) Lower 128 Bytes Internal RAM (Direct or Indirect Addressing) Figure 8.2 Data memory map The internal memory space is divided into three blocks, which are generally referred to as the lower 128, upper 128, and SFR space.

  • Page 48: Figure 8.3 Lower 128 Bytes Ram

    MC95FG0128A General purpose 80 bytes register 16 bytes Bit addressable (128bits) Register bank 3 8 bytes (8 bytes) Register bank 2 8 bytes (8 bytes) Register bank 1 8 bytes (8 bytes) Register bank 0 8 bytes (8 bytes) Figure 8.3 Lower 128 bytes RAM...

  • Page 49: Eeprom Data Memory And Xsram

    MC95FG0128A 8.3 EEPROM Data Memory and XSRAM MC95FG0128A has 4K bytes EEPROM Data memory and 8K bytes of XSRAM. This area has no relation with RAM/FLASH. It can read and write through SFR with 8-bit unit. For more information about EEPROM Data memory, see chapter 15.

  • Page 50: Sfr Map

    MC95FG0128A 8.4 SFR Map 8.4.1 SFR Map Summary Table 8-1 SFR Map Summary 0H/8H 1H/9H 2H/AH 3H/BH 4H/CH 5H/DH 6H/EH 7H/FH 2F58H FUSE_PKG FUSE_CAL2 FUSE_CAL1 FUSE_CAL0 FUSE_CONF TEST_B TEST_A 2F50H PSR0 PSR1 2F48H 2F40H 2F38H T5CR T5CR1 T5DRL T5DRH 2F30H...
  • Page 51 MC95FG0128A 8.4.2 Compiler Compatible SFR ACC (Accumulator) : E0H Initial value : 00H Accumulator B (B Register) : F0H Initial value : 00H B Register SP (Stack Pointer) : 81H Initial value : 07H Stack Pointer DPL (Data Pointer Low Byte) : 82H...
  • Page 52 MC95FG0128A DPH1 (Data Pointer High 1 Byte) : 85H DPH1 Initial value : 00H DPH1 Data Pointer High 1 Byte PSW (Program Status Word) : D0H Initial value : 00H Carry Flag Auxiliary Carry Flag General Purpose User-Definable Flag Register Bank Select bit 1...
  • Page 53 MC95FG0128A MEX1 (Memory Extension Register 1) : 94H CB19 CB18 CB17 CB16 NB19 NB18 NB17 NB16 Initial value : 00H CB[19:16] Current Bank NB[19:16] Next Bank note) This register records the ‘current ‘ and ‘next’ memory bank numbers for Program code.

  • Page 54: I/O Ports

    9. I/O Ports 9.1 I/O Ports The MC95FG0128A has eleven I/O ports (P0 ~ PA). Each port can be easily configured by software as I/O pin, internal pull up and open drain pin to meet various system configurations and design requirements.
  • Page 55 MC95FG0128A enabled P0[7:0], P7[7:0] pin toggles. The PCIx Register control which pins contribute to the pin change interrupts. 9.2.7 Port Selection Register (PSRx) PSRx registers prevent the input leakage current when ports are connected to analog inputs. If the bit of PSRx is ‘1’, the dynamic current path of the schmitt OR gate of the port is cut off and the digital...
  • Page 56 MC95FG0128A P5OD 2F11H P5 Open-drain Selection Register P5DB 2F1DH P5 Debounce Enable Register P6 Data Register P6IO P6 Direction Register P6PU 2F06H P6 Pull-up Resistor Selection Register P6OD 2F12H P6 Open-drain Selection Register P6DB 2F1EH P6 Debounce Enable Register P7 Data Register...

  • Page 57: Px Port

    MC95FG0128A 9.3 Px Port 9.3.1 Px Port Description Px is 8-bit I/O port. Px control registers consist of Data register (Px), direction register (PxIO), debounce enable register (PxDB), pull-up register selection register (PxPU), open-drain selection register (PxOD), pin change interrupt register (PCI0, PCI7) 9.3.2 Register description for Px...
  • Page 58 MC95FG0128A PxDB (Px Debounce Enable Register) : 2F18H ~ 2F22H Px7DB Px6DB Px5DB Px4DB Px3DB Px2DB Px1DB Px0DB Initial value : 00H PxDB[7:0] Configure debounce of Px port Disable Enable PCI0 (P0 Pin Change Interrupt Enable Register) : AEH PCI07...

  • Page 59: Interrupt Controller

    10. Interrupt Controller 10.1 Overview The MC95FG0128A supports up to 32 interrupt sources. The interrupts have separate enable register bits associated with them, allowing software control. They can also have four levels of priority assigned to them. The interrupt controller has following features:...

  • Page 60: External Interrupt

    MC95FG0128A 10.2 External Interrupt The external interrupt on INT0, INT1, INT2, INT3, INT4, INT5, INT6 and INT7 pins receive various interrupt request depending on the edge selection register EIEDGE (External Interrupt Edge register) and EIPOLA (External Interrupt Polarity register) as shown in Figure 10.1. Also each external interrupt source has control setting bits.

  • Page 61: Block Diagram

    MC95FG0128A 10.3 Block Diagram IEDS0 EIFLAG.0[A4 Priority High FLAG0 INT0 EIFLAG.1[A4 FLAG1 INT1 EIFLAG.2[A4 FLAG2 INT2 EIFLAG.3[A4 INT3 FLAG3 INT5 PCI (P0) USTAT0.5 [E5 USART0 Rx USTAT0.6 [E5 USART0 Tx SPISR.7 [D4 TCIR I2CMR.7 [DA USTAT1.5 [FD RXC1 USART1 Rx USTAT1.6 [FD...

  • Page 62: Interrupt Vector Table

    MC95FG0128A 10.4 Interrupt Vector Table The interrupt controller supports 32 interrupt sources as shown in the Table 10-2 below. When interrupt becomes service, long call instruction (LCALL) is executed in the vector address. Interrupt request 32 has a decided priority order.

  • Page 63: Figure 10.3 Interrupt Sequence Flow

    MC95FG0128A interrupt return instruction [RETI]. After generating interrupt, to go to interrupt service routine, the following process is progressed IE.EA Flag  1 IEx.y  1 Program Counter low Byte SP  SP + 1 M(SP)  (PCL) Saves PC value in order to continue...

  • Page 64: Effective Timing After Controlling Interrupt Bit

    MC95FG0128A 10.6 Effective Timing after Controlling Interrupt bit INTnE reg. & EA bit set Next Instruction Setting both EA bit and individual interrupt enable bit INTnE makes the pending interrupt active after executing the next instruction. Next Instruction Figure 10.4 Interrupt Enable Register effective Timing...

  • Page 65: Multi Interrupt

    MC95FG0128A 10.7 Multi Interrupt If two requests of different priority levels are received simultaneously, the request of higher priority level is serviced. If requests of the interrupt are received at the same time simultaneously, an interrupt polling sequence determines by hardware which request is serviced. However, multiple processing through software for special features is possible.

  • Page 66: Interrupt Enable Accept Timing

    MC95FG0128A 10.8 Interrupt Enable Accept Timing Max. 4 Machine Cycle 4 Machine Cycle System Clock Interrupt goes Active Interrupt Interrupt Processing Latched Interrupt Routine : LCALL & LJMP Figure 10.6 Interrupt Response Timing Diagram 10.9 Interrupt Service Routine Address Basic Interval Timer...

  • Page 67: Interrupt Timing

    MC95FG0128A 10.11 Interrupt Timing Interrupt sampled here CLP2 CLP1 CLP2 C1P1 C1P2 C2P1 C2P2 SCLK INT_SRC INTR_ACK LAST_CYC INTR_LCALL 8-Bit interrupt Vector INT_VEC {8’h00, INT_VEC} PROGA Figure 10.9 Timing chart of Interrupt Acceptance and Interrupt Return Instruction Interrupt source sampled at last cycle of the command. When sampling interrupt source, it is decided to low 8-bit of interrupt vector.
  • Page 68 MC95FG0128A priority than high interrupt number. If decided the priority, low interrupt number has a higher priority than high interrupt number in that group. 10.12.3 External Interrupt Flag Register (EIFLAG) The external interrupt flag register is set to ‘1’ when the external interrupt generating condition is satisfied.

  • Page 69: Interrupt Register Description

    MC95FG0128A 10.13 Interrupt Register Description The Interrupt Register is used for controlling interrupt functions. Also it has External interrupt control registers. The interrupt register consists of Interrupt Enable Register (IE), Interrupt Enable Register 1 (IE1), Interrupt Enable Register 2 (IE2), Interrupt Enable Register 3 (IE3), Interrupt Enable Register 4 (IE4) and Interrupt Enable Register 5 (IE5).
  • Page 70 MC95FG0128A INT10E Enable or disable USART1 Rx Interrupt Disable Enable INT9E Enable or disable I C Interrupt Disable Enable INT8E Enable or disable SPI0 Interrupt Disable Enable INT7E Enable or disable USART0 Tx Interrupt Disable Enable INT6E Enable or disable USART0 Rx Interrupt...
  • Page 71 MC95FG0128A Enable INT22E Enable or disable BIT Interrupt Disable Enable INT21E Enable or disable WDT Interrupt Disable Enable INT20E Enable or disable WT Interrupt Disable Enable INT19E Enable or disable EEPROM Interrupt Disable Enable INT18E Enable or disable ADC Interrupt...
  • Page 72 MC95FG0128A Disable Enable INT34E Reserved Disable Enable INT33E Reserved Disable Enable INT32E Reserved Disable Enable INT31E Enable or disable External Interrupt 7 Disable Enable INT30E Enable or disable External Interrupt 6 Disable enable IP (Interrupt Priority Register) : B8H Initial value : 00H...
  • Page 73 MC95FG0128A EIEDGE (External Interrupt Edge Register) : A5H EDGE7 EDGE6 EDGE5 EDGE4 EDGE3 EDGE2 EDGE1 EDGE0 Initial value : 00H Determines which type of edge or level sensitive interrupt may occ EDGE[7:0] Level (default) Edge EIPOLA (External Interrupt Polarity Register) : A6H...

  • Page 74: Peripheral Hardware

    MC95FG0128A 11. Peripheral Hardware 11.1 Clock Generator 11.1.1 Overview As shown in Figure 11.1, the clock generator produces the basic clock pulses which provide the system clock to be supplied to the CPU and the peripheral hardware. It contains main-frequency clock oscillator.
  • Page 75 MC95FG0128A 11.1.3 Register Map Table 11-1 Register Map Name Address Default Description SCCR System and Clock Control Register PLLCR PLL Control Register 11.1.4 Clock Generator Register description The Clock Generation Register uses clock control for system operation. The clock generation consists of System and Clock register.
  • Page 76 MC95FG0128A Note2) if XINENA bit in FUSE_CONF to ‘0’, XSTOP is fixed to ‘1’ X-Tal Oscillation enable X-Tal Oscillation disable (default) CS[1:0] Determine System Clock Note) by CBYS bit, reflection point is decided Description fINTRC INTRC (8 MHz) fXIN Main Clock (1~10 MHz) fSUB / fPLL (32.768 KHz, 1.38~20.185MHz)
  • Page 77 Because, to achieve lower power consumption in sub- active mode, MC95FG0128A has a smaller SUB-ACTIVE VDC(voltage Down Converter) which is automatically enable in sub-active mode and has only 1mA current capability while main VDC(for normal operation) is off.

  • Page 78: Bit

    11.2 BIT 11.2.1 Overview The MC95FG0128A has one 8-bit Basic Interval Timer that is free-run and can’t stop. Block diagram is shown in Figure 11.2. In addition, the Basic Interval Timer generates the time base for watchdog timer counting. It also provides a Basic interval timer interrupt (BITF).
  • Page 79 MC95FG0128A 11.2.4 Bit Interval Timer Register description The Bit Interval Timer Register consists of BIT Clock control register (BCCR) and Basic Interval Timer register (BITR). If BCLR bit set to ‘1’, BITR becomes ‘0’ and then counts up. After 1 machine cycle, BCLR bit is cleared as ‘0’...

  • Page 80: Wdt

    MC95FG0128A 11.3 WDT 11.3.1 Overview The watchdog timer rapidly detects the CPU malfunction such as endless looping caused by noise or the like, and resumes the CPU to the normal state. The watchdog timer signal for detecting malfunction can be selected either a reset CPU or an interrupt request. When the watchdog timer is not being used for malfunction detection, it can be used as a timer to generate an interrupt at fixed intervals.
  • Page 81 MC95FG0128A 11.3.4 Watch Dog Timer Register description The Watch dog timer (WDT) Register consists of Watch Dog Timer Register (WDTR), Watch Dog Timer Counter Register (WDTCR) and Watch Dog Timer Mode Register (WDTMR). 11.3.5 Register description for Watch Dog Timer...

  • Page 82: Figure 11.4 Wdt Interrupt Timing Waveform

    MC95FG0128A 11.3.6 WDT Interrupt Timing Waveform Source Clock BIT Overflow WDTCR[7:0] Counter Clear WDTR[7:0] WDTCL Occur Match WDTIF WDTR  0000_0011b Detect Interrupt WDTRESETB RESET Figure 11.4 WDT Interrupt Timing Waveform Aug 02, 2018 Ver.2.9...

  • Page 83: Figure 11.5 Watch Timer Block Diagram

    MC95FG0128A 11.4 WT 11.4.1 Overview The watch timer has the function for RTC (Real Time Clock) operation. It is generally used for RTC design. The internal structure of the watch timer consists of the clock source select circuit, timer counter circuit, output select circuit and watch timer mode register. To operate the watch timer, determine the input clock source, output interval and set WTEN to ‘1’...
  • Page 84 MC95FG0128A 11.4.4 Watch Timer Register description The watch timer register (WT) consists of Watch Timer Mode Register (WTMR), Watch Timer Counter Register (WTCR) and Watch Timer Register (WTR). As WTMR is 6-bit writable/readable register, WTMR can control the clock source (WTCK), interrupt interval (WTIN) and function enable/disable (WTEN).
  • Page 85 MC95FG0128A Clear WT Counter (auto clear after 1 Cycle) WTR[6:0] Set WT period WT Interrupt Interval=(fwck/2^14) x(7bit WT Value+1) Note) To guarantee proper operation, it is greater than 01H to write WTR. WTCR (Watch Timer Counter Register: Read Case) : 9EH...

  • Page 86: Timer/Pwm

    MC95FG0128A 11.5 Timer/PWM 11.5.1 8-bit Timer/Event Counter 0, 1 11.5.1.1 Overview Timer 0 and timer 1 can be used either two 8-bit timer/counter or one 16-bit timer/counter with combine them. Each 8-bit timer/event counter module has multiplexer, 8-bit timer data register, 8-bit counter register, mode register, input capture register, comparator.

  • Page 87: Figure 11.6 8 Bit Timer/Event Counter2, 3 Block Diagram

    MC95FG0128A 11.5.1.2 8 Bit Timer/Counter Mode The 8-bit Timer/Counter Mode is selected by control registers as shown in Figure 11.6. ADDRESS : B2 T0CR T0EN T0PE CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST INITIAL VALUE : 0000_0000 ADDRESS : B4 T1CR...

  • Page 88: Figure 11.7 Timer/Event Counter0, 1 Example

    MC95FG0128A Match with T0DR/T1DR T0DR/T1DR Value Count Pulse Period Up-count Interrupt Period TIME x (n+1) Timer 0, 1 (T0IF, T1IF) Occur Occur Occur Interrupt Interrupt Interrupt Interrupt Figure 11.7 Timer/Event Counter0, 1 Example T0DR/T1DR Disable Enable Value Clear&Start STOP Up-count...

  • Page 89: Figure 11.9 16 Bit Timer/Event Counter0, 1 Block Diagram

    MC95FG0128A 11.5.1.3 16 Bit Timer/Counter Mode The timer register is being run with all 16bits. A 16-bit timer/counter register T0, T1 are incremented from 0003H to FFFFH until it matches T0DR, T1DR and then resets to 0000H. the match output generates the Timer 0 interrupt ( no timer 1 interrupt).

  • Page 90: Figure 11.10 8-Bit Capture Mode For Timer0, 1

    MC95FG0128A ADDRESS : B2 T0ST T0CR T0EN T0PE CAP0 T0CK2 T0CK1 T0CK0 T0CN INITIAL VALUE : 0000_0000 ADDRESS : B4 T1CR POL1 16BIT PWM1E CAP1 T1CK1 T1CK0 T1CN T1ST INITIAL VALUE : 0000_0000 T0ST T0CN ÷2 8-bit Timer0 Counter ÷4 Clear ÷16...

  • Page 91: Figure 11.11 Input Capture Mode Operation Of Timer 0, 1

    MC95FG0128A CDR0, CDR1 Load T0/T1 Value Count Pulse Period Up-count TIME Ext. INT0,1PIN Interrupt Request (INT0F,INT1F) Interrupt Interval Period Figure 11.11 Input Capture Mode Operation of Timer 0, 1 T0, T1 Interrupt Request (T0IF,T1IF) Ext. INT0,1 PIN Interrupt Request (INT0F,INT1F) Interrupt Interval Period = FF Figure 11.12 Express Timer Overflow in Capture Mode...

  • Page 92: Figure 11.13 16-Bit Capture Mode Of Timer 0, 1

    MC95FG0128A 11.5.1.5 16 Bit Capture Mode The 16-bit capture mode is the same operation as 8-bit capture mode, except that the timer register uses 16 bits. The clock source is selected from T0CK[2:0] and T1CK[1:0] must set 11b and 16BIT2 bit must set to ‘1’.

  • Page 93: Figure 11.14 Pwm Mode

    MC95FG0128A Table 11-7 PWM Frequency vs. Resolution at 8 Mhz Frequency Resolution T1CK[1:0]=00 (125ns) T1CK[1:0]=01 (250ns) T1CK[1:0]=10 (2us) 10 Bit 7.8KHz 3.9KHz 0.49KHz 9 Bit 15.6KHz 7.8KHz 0.98KHz 8 Bit 31.2KHz 15.6KHz 1.95KHz 7 Bit 62.4KHz 31.2KHz 3.91KHz The POL bit of T1CR register decides the polarity of duty cycle. If the duty value is set same to the period value, the PWM output is determined by the bit POL (1: High, 0: Low).

  • Page 94: Figure 11.15 Example Of Pwm At 4Mhz

    MC95FG0128A Source Clock T1/PWM1 POL = 1 T1/PWM1 POL = 0 Duty Cycle(1+80 )X250ns = 32.25us )X250ns = 256us  3.9kHz Period Cycle(1+3FF PW1H3 PW1H2 T1PPR(8 Bit) T1CR[1:0] = 00 T1PWHR = 03 T1PPR = FF PW1H1 PW1H0 T1PDR(8 Bit) T1PDR = 80 Figure 11.15 Example of PWM at 4MHz...
  • Page 95 MC95FG0128A 11.5.1.7 8-Bit (16 Bit) Compare Output Mode If the T1 (T0+T1) value and the T1DR (T0DR+T1DR) value are matched, T1/PWM1 port outputs. The output is 50:50 of duty square wave, the frequency is following Oscillator Frequency   ...
  • Page 96 MC95FG0128A T0EN Control Timer 0 Timer 0 disable Timer 0 enable T0_PE Control Timer 0 Output port Timer 0 Output disable Timer 0 Output enable CAP0 Control Timer 0 operation mode Timer/Counter mode Capture mode T0CK[2:0] Select Timer 0 clock source. Fx is main system clock frequency...
  • Page 97 MC95FG0128A CDR0[7:0] T0 Capture data T1CR (Timer 1 Mode Count Register) : B4H 16BIT PWM1E CAP1 T1CK1 T1CK0 T1CN T1ST Initial value : 00H Configure PWM polarity Negative (Duty Match: Clear) Positive (Duty Match: Set) 16BIT Select Timer 1 8/16Bit...
  • Page 98 MC95FG0128A T1 (Timer 1 Register: Read Case) : B6H Initial value : 00H T1[7:0] T1 Counter Period data T1PDR (Timer 1 PWM Duty Register) : B6H T1PD7 T1PD6 T1PD5 T1PD4 T1PD3 T1PD2 T1PD1 T1PD0 Initial value : 00H T1PD[7:0] T1 PWM Duty data Note) only write, when PWM1E ‘1’...

  • Page 99: Figure 11.17 Timerx 16-Bit Mode Block Diagram

    MC95FG0128A 11.5.2 16-bit Timer/Event Counter 2, 3, 4, 5 11.5.2.1 Overview The 16-bit timer x(2~5) consists of Multiplexer, Timer Data Register High/Low, Timer Register High/Low, Timer Mode Control Register, PWM Duty High/Low, PWM Period High/Low Register It is able to use internal 16-bit timer/ counter without a port output function.

  • Page 100: Figure 11.18 16-Bit Capture Mode Of Timer X

    MC95FG0128A 11.5.2.3 16-Bit Capture Mode The timer X(2~5) capture mode is set by CAPx as ‘1’ in TxCR register. The clock is same source as Output Compare mode. The interrupt occurs at TxH, TxL and TxDRH, TxDRL matching time. The capture result is loaded into CDRxH, CDRxL.

  • Page 101: Figure 11.19 Pwm Mode

    MC95FG0128A Table 11-9 PWM Frequency vs. Resolution at 8 Mhz Frequency Resolution TxCK[2:0]=000 (125ns) TxCK[2:0]=010 (500ns) TxCK[2:0]=011 (1us) 16-bit 122.070Hz 30.469Hz 15.259Hz 15-bit 244.141Hz 60.938Hz 30.518Hz 10-bit 7.8125KHz 1.95KHz 976.563Hz 9-bit 15.625KHz 3.9KHz 1.953KHz 8-bit 31.25KHz 7.8KHz 3.906KHz The POL bit of TxCR register decides the polarity of duty cycle. If the duty value is set same to the period value, the PWM output is determined by the bit POL (1: High, 0: Low).

  • Page 102: Figure 11.20 Example Of Pwm At 8Mhz

    MC95FG0128A Source Clock Tx/PWMx POL0 = 1 Tx/PWMx POL0 = 0 Duty Cycle(1+0080 )X500ns = 64.50us )X500ns = 512us  1.95kHz Period Cycle(1+03FF TxCK[2:0] = 01 PWMxHPR(8-bit) PWMxLPR(8-bit) PCLK PWMxHPR = 03 PWMxLPR = FF PWMxHDR = 00 PWMxHDR(8-bit) PWMxLDR(8-bit) PWMxLDR = 80 Figure 11.20 Example of PWM at 8MHz...
  • Page 103 MC95FG0128A T3DRH Timer 3 Data Register High PWM3HPR PWM 3 Period High Data Register T4CR Timer 4 Mode Control Register T4CR1 Timer 4 Mode Control Register 1 Timer 4 Low Register PWM4LDR PWM 4 Duty Low Register CDR4 L Timer 4 Capture Data Low Register...
  • Page 104 MC95FG0128A 11.5.2.7 Register description for Timer/Counter 2~5 T2CR, T3CR, T4CR, T5CR (Timer 2~5 Mode Control Register): BAH, C2H, CAH, 2F38H TxEN PWMxE CAPx TxCK2 TxCK1 TxCK0 TxCN TxST Initial value : 00 TxEN Control Timer X Timer X enable PWMxE...
  • Page 105 MC95FG0128A Timer X Output enable Configure PWM polarity Negative (Duty Match: Clear) Positive (Duty Match: Set) T2L, T3L, T4L, T5L (Timer 2~5 Low Register, Read Case) : BCH, C4H, CCH, 2F3AH TxL7 TxL6 TxL5 TxL4 TxL3 TxL2 TxL1 TxL0 Initial value : 00 TxL[7:0] TxL Counter Period Low data.
  • Page 106 MC95FG0128A CDRxH[7:0] Tx Capture High data PWM2HDR, PWM3HDR, PWM4HDR, PWM5HDR (PWM 2~5 High Duty Register, Write Case) : BDH, C5H, CDH, 2F3BH PWMxHD7 PWMxHD6 PWMxHD5 PWMxHD4 PWMxHD3 PWMxHD2 PWMxHD1 PWMxHD0 Initial value : 00 PWMxHD[7:0] Tx PWM Duty High data Note) only write, when PWMxE ‘1’...
  • Page 107 MC95FG0128A 11.5.3 Timer Interrupt Status Register (TMISR) 11.5.3.1 Register description for TMISR TMISR (Timer Interrupt Status Register) : D5H TMIF5 TMIF4 TMIF3 TMIF2 TMIF1 TMIF0 Initial value : 00H TMIF5 Timer 5 Interrupt Flag No Timer 5 interrupt Timer 5 interrupt occurred, write “1” to clear interrupt flag...

  • Page 108: Buzzer Driver

    MC95FG0128A 11.6 Buzzer Driver 11.6.1 Overview The Buzzer consists of 8 Bit Counter and BUZDR (Buzzer Data Register), BUZCR (Buzzer Control Register). The Square Wave (61.035Hz~125 KHz, @8MHz) gets out of P12/BUZ pin. BUZDR (Buzzer Data Register) controls the Buzzer frequency (look at the following expression). In the BUZCR (Buzzer Control Register), BUCK[1:0] selects source clock divided from prescaler.
  • Page 109 MC95FG0128A 11.6.3 Register Map Table 11-12 Register Map Name Address Default Description BUZDR Buzzer Data Register BUZCR Buzzer Control Register 11.6.4 Buzzer Driver Register description Buzzer Driver consists of Buzzer Data Register (BUZDR), Buzzer Control Register (BUZCR). 11.6.5 Register description for Buzzer Driver...

  • Page 110: Usart

    MC95FG0128A 11.7 USART 11.7.1 Overview The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device. The main features are listed below. - Full Duplex Operation (Independent Serial Receive and Transmit Registers) - Asynchronous or Synchronous Operation...

  • Page 111: Figure 11.22 Usart Block Diagram

    MC95FG0128A 11.7.2 Block Diagram UBAUD SCLK Baud Rate Generator Master Clock Sync Logic Control UMSEL[1:0] Rx Interrupt RXD/ MISO Clock Control Recovery Data Receive Shift Register Recovery (RXSR) UMSEL1&UMSEL0 DOR/PE/FE UDATA[0] Master Checker (Rx) UDATA[1] Stop bit UMSEL0 (Rx) UPM0...

  • Page 112: Figure 11.23 Clock Generation Block Diagram

    MC95FG0128A 11.7.3 Clock Generation UBAUD SCLK (UBAUD+1) Prescaling Up-Counter txclk SCLK MASTER Edge Sync Register UMSEL0 Detector UCPOL rxclk Figure 11.23 Clock Generation Block Diagram The Clock generation logic generates the base clock for the Transmitter and Receiver. The USART supports four modes of clock operation and those are Normal Asynchronous, Double Speed Asynchronous, Master Synchronous and Slave Synchronous.

  • Page 113: Figure 11.24 Synchronous Mode Xckn Timing

    MC95FG0128A 11.7.4 External Clock (XCK) External clocking is used by the synchronous or spi slave modes of operation. External clock input from the XCK pin is sampled by a synchronization logic to remove meta-stability. The output from the synchronization logic must then pass through an edge detector before it can be used by the Transmitter and Receiver.

  • Page 114: Figure 11.25 Frame Format

    MC95FG0128A 11.7.6 Data format A serial frame is defined to be one character of data bits with synchronization bits (start and stop bits), and optionally a parity bit for error checking. The USART supports all 30 combinations of the following as valid frame formats.
  • Page 115 MC95FG0128A ^ … ^ D : Parity bit using even parity even : Parity bit using odd parity : Data bit n of the character 11.7.8 USART Transmitter The USART Transmitter is enabled by setting the TXE bit in UCTRLx1 register. When the Transmitter is enabled, the normal port operation of the TXD pin is overridden by the serial output pin of USART.
  • Page 116 MC95FG0128A 11.7.8.3 Parity Generator The Parity Generator calculates the parity bit for the sending serial frame data. When parity bit is enabled (UPM[1]=1), the transmitter control logic inserts the parity bit between the MSB and the first stop bit of the sending frame.
  • Page 117 MC95FG0128A When the Receive Complete Interrupt Enable (RXCIE) bit in the UCTRLx2 register is set and Global Interrupt is enabled, the USART Receiver Complete Interrupt is generated while RXC flag is set. The USART Receiver has three error flags which are Frame Error (FE), Data OverRun (DOR) and Parity Error (PE).

  • Page 118: Figure 11.26 Start Bit Sampling

    MC95FG0128A START IDLE BIT0 Sample (U2X = 0) Sample (U2X = 1) Figure 11.26 Start Bit Sampling When the Receiver is enabled (RXE=1), the clock recovery logic tries to find a high to low transition on the RXD line, the start bit condition. After detecting high to low transition on RXD line, the clock recovery logic uses samples 8,9, and 10 for Normal mode, and samples 4, 5, and 6 for Double Speed mode to decide if a valid start bit is received.

  • Page 119: Figure 11.28 Stop Bit Sampling And Next Start Bit Sampling

    MC95FG0128A STOP 1 Sample (U2X = 0) Sample (U2X = 1) Figure 11.28 Stop Bit Sampling and Next Start Bit Sampling 11.7.10 SPI Mode The USART can be set to operate in industrial standard SPI compliant mode. The SPI mode has the following features.

  • Page 120: Figure 11.29 Spi Clock Formats When Ucpha=0

    MC95FG0128A (UCPOL=0) (UCPOL=1) SAMPLE MOSI MSB First … BIT7 BIT6 BIT2 BIT1 BIT0 LSB First … BIT0 BIT1 BIT5 BIT6 BIT7 MISO /SS OUT (MASTER) /SS IN (SLAVE) Figure 11.29 SPI Clock Formats when UCPHA=0 When UCPHA=0, the slave begins to drive its MISO output with the first data bit value when SS goes to active low.

  • Page 121: Figure 11.30 Spi Clock Formats When Ucpha=1

    MC95FG0128A (UCPOL=0) (UCPOL=1) SAMPLE MOSI … MSB First BIT7 BIT6 BIT2 BIT1 BIT0 … LSB First BIT0 BIT1 BIT5 BIT6 BIT7 MISO /SS OUT (MASTER) /SS IN (SLAVE) Figure 11.30 SPI Clock Formats when UCPHA=1 When UCPHA=1, the slave begins to drive its MISO output when SS goes active low, but the data is not defined until the first XCK edge.
  • Page 122 MC95FG0128A UCTRL11 USART Control 1 Register 1 UCTRL12 USART Control 2 Register 1 UCTRL13 USART Control 3 Register 1 USTAT1 USART Status Register 1 UBAUD1 USART Baud Rate Generation Register 1 UDATA1 USART Data Register 2 UCTRL21 2F28H USART Control 1 Register 2...
  • Page 123 MC95FG0128A Odd Parity USIZE[2:0] When in asynchronous or synchronous mode of operation, selects the length of data bits in frame. USIZE2 USIZE1 USIZE0 Data Length 5 bit 6 bit 7 bit 8 bit Reserved Reserved Reserved 9 bit UDORD This bit is in the same bit position with USIZE1. In SPI mode, when set to one the MSB of the data byte is transmitted first.
  • Page 124 MC95FG0128A Interrupt from Wake is inhibited When WAKE is set, request an interrupt Enables the transmitter unit. Transmitter is disabled Transmitter is enabled Enables the receiver unit. Receiver is disabled Receiver is enabled USARTEN Activate USART module by supplying clock.
  • Page 125 MC95FG0128A USTATx (USART Status Register) : E5H, FDH, 2F2BH, 2F33H UDRE WAKE SOFTRST Initial value : 80H UDRE The UDRE flag indicates if the transmit buffer (UDATA) is ready to be loaded with new data. If UDRE is ‘1’, it means the transmit buffer is empty and can hold one or two new data.
  • Page 126 MC95FG0128A UBAUDx(USART Baud-Rate Generation Register) : E6H, FEH, 2F2CH, 2F34H UBAUD7 UBAUD6 UBAUD5 UBAUD4 UBAUD3 UBAUD2 UBAUD1 UBAUD0 Initial value : FFH UBAUD [7:0] The value in this register is used to generate internal baud rate in asynchronous mode or to generate XCK clock in synchronous or spi mode.
  • Page 127 MC95FG0128A 11.7.14 Baud Rate setting (example) Table 11-16 Examples of UBAUD Settings for Commonly Used Oscillator Frequencies fOSC=1.00MHz fOSC=1.8432MHz fOSC=2.00MHz Baud U2X=0 U2X=1 U2X=0 U2X=1 U2X=0 U2X=1 Rate UBAUD ERROR UBAUD ERROR UBAUD ERROR UBAUD ERROR UBAUD ERROR UBAUD ERROR 2400 0.2%...

  • Page 128: Spi

    11.8 SPI 11.8.1 Overview There is Serial Peripheral Interface (SPI) one channel in MC95FG0128A. The SPI allows synchronous serial data transfer between the external serial devices. It can do Full-duplex communication by 4-wire (MOSI, MISO, SCK, SS), support Master/Slave mode, can select serial clock (SCK) polarity, phase and whether LSB first data transfer or MSB first data transfer.
  • Page 129 MC95FG0128A 11.8.3 Data Transmit / Receive Operation User can use SPI for serial data communication by following step 1. Select SPI operation mode(master/slave, polarity, phase) by control register SPICR. 2. When the SPI is configured as a Master, it selects a Slave by SS signal (active low).

  • Page 130: Figure 11.32 Spi Transmit/Receive Timing Diagram At Cpha = 0

    MC95FG0128A 11.8.5 Timing Waveform SCKx (CPOL=0) SCKx (CPOL=1) MISOx/MOSIx (Output) MOSxI/MISOx (Input) TCIR SS_HIGH Figure 11.32 SPI Transmit/Receive Timing Diagram at CPHA = 0 SCKx (CPOL=0) SCKx (CPOL=1) MISOx/MOSIx (Output) MOSIx/MISOx (Input) TCIR SS_HIGH Figure 11.33 SPI Transmit/Receive Timing Diagram at CPHA = 1 11.8.6 Register Map...
  • Page 131 MC95FG0128A 11.8.7 SPI Register description The SPI Register consists of SPI Control Register (SPICRx), SPI Status Register (SPISRx) and SPI Data Register (SPIDRx) 11.8.8 Register description for SPI SPICRx (SPI Control Register) : D2H, 92H SPIEN FLSB CPOL CPHA DSCR...
  • Page 132 MC95FG0128A SPIDRx (SPI Data Register) : D3H, 93H SPIDR7 SPIDR6 SPIDR5 SPIDR4 SPIDR3 SPIDR2 SPIDR1 SPIDR0 Initial value : 00H SPIDR [7:0] SPI data register. Although you only use reception, user must write any data in here to start the SPI operation.

  • Page 133: I 2 C

    MC95FG0128A 11.9 I 11.9.1 Overview The I C is one of industrial standard serial communication protocols, and which uses 2 bus lines Serial Data Line (SDA) and Serial Clock Line (SCL) to exchange data. Because both SDA and SCL lines are open-drain output, each line needs pull-up resistor. The features are as shown below.

  • Page 134: Figure 11.35 Bit Transfer On The I C-Bus

    MC95FG0128A Data line Stable: Change of Data Data valid allowed exept S, Sr, P Figure 11.35 Bit Transfer on the I C-Bus 11.9.4 Start / Repeated Start / Stop One master can issue a START (S) condition to notice other devices connected to the SCL, SDA lines that it will use the bus.

  • Page 135: Figure 11.37 Data Transfer On The I C-Bus

    MC95FG0128A Acknowledgement Acknowledgement Signal form Slave Signal form Slave Byte Complete, Clock line held low while Interrupt within Device interrupts are served. START or Repeated STOP or Repeated START Condition START Condition Figure 11.37 Data Transfer on the I C-Bus 11.9.6 Acknowledge...

  • Page 136: Figure 11.39 Clock Synchronization During Arbitration Procedure

    MC95FG0128A line if another clock is still within its LOW period. In this way, a synchronized SCL clock is generated with its LOW period determined by the device with the longest clock LOW period, and its HIGH period determined by the one with the shortest clock HIGH period.
  • Page 137 MC95FG0128A Note that when a I C interrupt is generated, IIF flag in I2CMR register is set, it is cleared by writing an arbitrary value to I2CSR. When I C interrupt occurs, the SCL line is hold LOW until writing any value to I2CSR.
  • Page 138 MC95FG0128A MLOST bit in I2CSR is set. If then, I C waits in idle state. When the data in I2CDR is transmitted completely, I C generates TEND interrupt. C can choose one of the following cases regardless of the reception of ACK signal from slave.

  • Page 139: Figure 11.41 Formats And States In The Master Transmitter Mode

    MC95FG0128A The next figure depicts above process for master transmitter operation of I Master S or Sr SLA+R Receiver SLA+W 0x86 0x22 STOP 0x0E 0x87 LOST DATA STOP LOST LOST& Slave Receiver (0x1D) 0x0F 0x1D 0x1F or Transmitter (0x1F) 0x46...
  • Page 140 MC95FG0128A 11.9.8.2 Master Receiver To operate I C in master receiver, follow the recommended steps below. 1. Enable I C by setting IICEN bit in I2CMR. This provides main clock to the peripheral. 2. Load SLA+R into the I2CDR where SLA is address of slave device and R is transfer direction from the viewpoint of the master.

  • Page 141: Figure 11.42 Formats And States In The Master Receiver Mode

    MC95FG0128A STOP bit in I2CMR. 4) No ACK signal is detected, and master transmits repeated START condition. In this case, load SLA+R/W into the I2CDR and set the START bit in I2CMR. After doing one of the actions above, write arbitrary value to I2CSR to release SCL line. In case of 1) and 2), move to step 7.
  • Page 142 MC95FG0128A 11.9.8.3 Slave Transmitter To operate I C in slave transmitter, follow the recommended steps below. 1. If the main operating clock (SCLK) of the system is slower than that of SCL, load value 0x00 into I2CSDAHR to make SDA change within one system clock period from the falling edge of SCL.

  • Page 143: Figure 11.43 Formats And States In The Slave Transmitter Mode

    MC95FG0128A The next figure shows flow chart for handling slave transmitter function of I IDLE S or Sr SLA+R GCALL 0x97 0x1F LOST& 0x17 DATA 0x22 STOP 0x47 0x46 IDLE From master to slave / Interrupt, SCL line is held low...
  • Page 144 MC95FG0128A 3. When a START condition is detected, I C receives one byte of data and compares it with SLA bits in I2CSAR. If the GCALLEN bit in I2CSAR is enabled, I C compares the received data with value 0x00, the general call address.

  • Page 145: Figure 11.44 Formats And States In The Slave Receiver Mode

    MC95FG0128A IDLE S or Sr SLA+W GCALL 0x95 0x1D LOST& 0x15 DATA 0x20 STOP 0x44 0x45 IDLE From master to slave / Interrupt, SCL line is held low Master command or Data Write From slave to master Interrupt after stop command...
  • Page 146 MC95FG0128A 11.9.10 I C Register description C Registers are composed of I C Mode Control Register (I2CMR), I C Status Register (I2CSR), SCL Low Period Register (I2CSCLLR), SCL High Period Register (I2CSCLHR), SDA Hold Time Register (I2CSDAHR), I C Data Register (I2CDR), and I C Slave Address Register (I2CSAR).
  • Page 147 MC95FG0128A I2CSR (I C Status Register) : DBH GCALL TEND STOP SSEL MLOST BUSY TMODE RXACK Initial value : 00H GCALL This bit has different meaning depending on whether I C is master or slave. Note 1) When I C is a master, this bit represents whether it received AACK (Address ACK) from slave.
  • Page 148 MC95FG0128A SCLL[7:0] This register defines the LOW period of SCL when I C operates in master mode. The base clock is SCLK, the system clock, and the × (4 × SCLL + 1) where period is calculated by the formula : t SCLK is the period of SCLK.
  • Page 149 MC95FG0128A GCALLEN This bit decides whether I C allows general call address or not when I C operates in slave mode. Ignore general call address Allow general call address I2CSAR1 (I C Slave Address Register 1) : D6H SLA7 SLA6...

  • Page 150: 12-Bit A/D Converter

    MC95FG0128A 11.10 12-Bit A/D Converter 11.10.1 Overview The analog-to-digital converter (A/D) allows conversion of an analog input signal to a corresponding 12-bit digital value. The A/D module has tenth analog inputs. The output of the multiplex is the input into the converter, which generates the result via successive approximation. The A/D module has four...

  • Page 151: Figure 11.46 A/D Analog Input Pin Connecting Capacitor

    MC95FG0128A Analog Analog AN0 ~ AN14 AVDD Input Power Input 0~1000pF 22uF Figure 11.46 A/D Analog Input Pin Figure 11.47 A/D Power(AVDD) Pin Connecting Capacitor Connecting Capacitor 11.10.3 ADC Operation Align bit set “0” ADCO11 ADCO10 ADCO9 ADCO8 ADCO7 ADCO6...

  • Page 152: Figure 11.49 Converter Operation Flow

    MC95FG0128A SET ADCM2 Select ADC Clock & Data Align Bit. SET ADCM ADC enable & Select AN Input Channel. Converting START Start ADC Conversion. If Conversion is completed, AFLG is set “1” and ADC AFLAG = 1? interrupt is occurred.
  • Page 153 MC95FG0128A 11.10.6 Register description for ADC ADCM (A/D Converter Mode Register) : 9AH STBY ADST REFSEL AFLAG ADSEL3 ADSEL2 ADSEL1 ADSEL0 Initial value : 8FH STBY Control operation of A/D standby (power down) ADC module enable ADC module disable (power down) ADST Control A/D Conversion stop/start.
  • Page 154 MC95FG0128A ADDL[11:8] LSB align, A/D Converter High result (4-bit) ADCRL (A/D Converter Result Low Register) : 9CH ADDM3 ADDM2 ADDM1 ADDM0 ADDL7 ADDL6 ADDL5 ADDL4 ADDL3 ADDL2 ADDL1 ADDL0 Initial value : xxH ADDM[3:0] MSB align, A/D Converter Low result (4-bit)

  • Page 155: Calculator_Ai

    MC95FG0128A 11.11 CALCULATOR_AI 11.11.1 Introduction The CALCULATOR_AI block is an integrated version of multiplier and divider data path block. All operation is performed with signed extension (signed multiplication, signed division). The multiplication needs only one clock cycle, but the division is performed during 32 clock cycles. You can use the EOD (End of Division) flag bit to control the division calculation flow.
  • Page 156 MC95FG0128A 11.11.2 Calculator Registers CAL_CNTR (Calculator Control Register) : F7H DIV_BY_0 Initial value : 02H DIV_BY_0 Indicate if Divisor equals 0 Divisor is not 0 Divisor is 0 End of Division Note) Multiplication needs only one clock cycle. Note) Division needs 32 clock cycles...
  • Page 157 MC95FG0128A 11.11.3 Calculator Library 11.11.3.1 Signed Multiplication __sfr __at (0xF7) CAL_CNTR; __sfr __at (0xEE) CAL_ADDR; __sfr __at (0xEF) CAL_DATA; #define CAL_DIV_START 0x01 #define CAL_DIV_DONE 0x02 #define CAL_DIV_BY_0 0x04 long L_mul( short a, short b ) { long mul_o; mul_o = 0;...
  • Page 158 MC95FG0128A #define CAL_DIV_BY_0 0x04 void L_div( long a, short b, long* q, short* r) { long div_q; short div_r; div_q = 0; div_r = 0; CAL_ADDR = 8; // currently point to DA[31:24] CAL_DATA = a >> 24; // DA[31:24]<-a[31:24], ADDR<-ADDR+1 CAL_DATA = a >>...

  • Page 159: Power Down Operation

    12. Power Down Operation 12.1 Overview The MC95FG0128A has three power-down modes to minimize the power consumption of the device. In power down mode, power consumption is reduced considerably. The device provides three kinds of power saving functions, IDLE, STOP1 and STOP2 mode. In three modes, program is stopped.

  • Page 160: Idle Mode

    MC95FG0128A 12.3 IDLE mode The power control register is set to ‘01h’ to enter the IDLE Mode. In this mode, the internal oscillation circuits remain active. Oscillation continues and peripherals are operated normally but CPU stops. It is released by reset or interrupt. To be released by interrupt, interrupt should be enabled before IDLE mode.

  • Page 161: Figure 12.3 Stop Mode Release Timing By External Interrupt

    MC95FG0128A The source for exit from STOP mode is hardware reset and interrupts. The reset re-defines all the control registers. When exit from STOP mode, enough oscillation stabilization time is required to normal operation. Figure 12.3 shows the timing diagram. When released from STOP mode, the Basic interval timer is activated on wake-up.

  • Page 162: Release Operation Of Stop1, 2 Mode

    MC95FG0128A 12.5 Release Operation of STOP1, 2 Mode After STOP1, 2 mode is released, the operation begins according to content of related interrupt register just before STOP1, 2 mode start (Figure 12.5). Interrupt Enable Flag of All (EA) of IE should be set to `1`.
  • Page 163 MC95FG0128A 12.5.1 Register Map Table 12-2 Register Map Name Address Default Description PCON Power Control Register 12.5.2 Power Down Operation Register description The Power Down Operation Register consists of the Power Control Register (PCON). 12.5.3 Register description for Power Down Operation...

  • Page 164: Reset

    MC95FG0128A 13. RESET 13.1 Overview The MC95FG0128A has reset by external RESETB pin. The following is the hardware setting value. Table 13-1 Reset state On Chip Hardware Initial Value Program Counter (PC) 0000h Accumulator Stack Pointer (SP) Peripheral Clock Control Register...

  • Page 165: Reset Noise Canceller

    MC95FG0128A 13.4 RESET Noise Canceller The Figure 13.2 is the Noise canceller diagram for Noise cancel of RESET. It has the Noise cancel value of about 7us (@V =5V) to the low input of System Reset. t < T t < T t >...

  • Page 166: Figure 13.4 Internal Reset Release Timing On Power-Up

    MC95FG0128A Slow VDD Rise Time, max 0.02v/ms =1.4V (Typ) nPOR BIT Overflows (Internal Signal) BIT Starts Internal RESETb Oscillation Figure 13.4 Internal RESET Release Timing On Power-Up Counting for config read start after POR is released Internal nPOR PAD RESETB (R20) “H”...

  • Page 167: Figure 13.6 Boot Process Wave Form

    MC95FG0128A :VDD Input :Internal OSC ⑥ ④ Reset Release Config Read ② ⑤ ⑦ ① ③ Figure 13.6 Boot Process Wave Form Table 13-2 Boot Process Description Process Description Remarks ① -No Operation -1st POR level Detection ② -about 1.4V ~ 1.5V -Internal OSC (125KHz) ON - (INT-OSC125KHz/32)×30h Delay section (=12ms)

  • Page 168: External Resetb Input

    MC95FG0128A 13.6 External RESETB Input The External RESETB is the input to a Schmitt trigger. A reset in accomplished by holding the reset pin low for at least 7us over, within the operating voltage range and oscillation stable, it is applied, and the internal state is initialized.

  • Page 169: Brown Out Detector Processor

    MC95FG0128A 13.7 Brown Out Detector Processor The MC95FG0128A has an On-chip Brown-out detection circuit for monitoring the VDD level during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be selected by BODLS[1:0] bit to be 1.6V, 2.5V, 3.6V or 4.2V. In the STOP mode, this will contribute significantly to the total current consumption.

  • Page 170: Figure 13.11 Configuration Timing When Bod Reset

    MC95FG0128A “H” “H” Internal nPOR “H” PAD RESETB (R20) BOD_RESETB .. 2F 30 BIT (for Config) 00 01 02 BIT (for Reset) 3F 40 00 01 02 03 01 02 250us X 30h = about 12ms Config Read 250us X 40h = about 16ms...
  • Page 171 MC95FG0128A Power-On Reset flag bit. The bit is reset by writing ‘0’ to this bit. PORF No detection Detection External Reset flag bit. The bit is reset by writing ‘0’ to this bit or by EXTRF Power ON reset. No detection Detection Watch Dog Reset flag bit.

  • Page 172: On-Chip Debug System

    14. On-chip Debug System 14.1 Overview 14.1.1 Description On-chip debug System (OCD) of MC95FG0128A can be used for programming the non-volatile memories and on-chip debugging. Detailed descriptions for programming via the OCD interface can be found in the following chapter.

  • Page 173: Two-Pin External Interface

    MC95FG0128A Target MCU internal circuit Format converter DSCL Control DSDA DBG Register Address bus Internal data bus User I/O Code memory Data memory Peripheral - SRAM - Flash - EEPROM Figure 14.1 Block Diagram of On-chip Debug System 14.2 Two-pin external interface 14.2.1 Basic transmission packet...

  • Page 174: Figure 14.2 10-Bit Transmission Packet

    MC95FG0128A Figure 14.2 10-bit transmission packet 14.2.2 Packet transmission timing 14.2.2.1 Data transfer DSDA acknowledgement acknowledgement signal from receiver signal from receiver DSCL START STOP Figure 14.3 Data transfer on the twin bus Aug 02, 2018 Ver.2.9...

  • Page 175: Figure 14.4 Bit Transfer On The Serial Bus

    MC95FG0128A 14.2.2.2 Bit transfer DSDA DSCL data line change stable of data : data valid allowed except Start and Stop Figure 14.4 Bit transfer on the serial bus 14.2.2.3 Start and stop condition DSDA DSDA DSCL DSCL START condition STOP condition Figure 14.5 Start and stop condition...

  • Page 176: Figure 14.7 Clock Synchronization During Wait Procedure

    MC95FG0128A Acknowledge bit Acknowledge bit transmission transmission Minimum 500ns wait HIGH start HIGH Host PC DSCL OUT Start wait Target Device DSCL OUT minimum 1 T SCLK for next byte Maximum 5 T SCLK transmission DSCL Internal Operation Figure 14.7 Clock synchronization during wait procedure 14.2.3 Connection of transmission...

  • Page 177: Memory Programming

    15. Memory Programming 15.1 Overview 15.1.1 Description MC95FG0128A incorporates flash and data EEPROM memory to which a program can be written, erased, and overwritten while mounted on the board. Also, data EEPROM can be programmed or erased in user program.
  • Page 178 MC95FG0128A 15.2.2 Register description for Flash and EEPROM FEMR (Flash and EEPROM Mode Register) : EAH FSEL ESEL ERASE PBUFF OTPE FEEN Initial value : 00H FSEL Select flash memory. Deselect flash memory Select flash memory ESEL Select data EEPROM...
  • Page 179 MC95FG0128A Don’t exit from program mode Don’t exit from program mode Don’t exit from program mode Exit from program mode WRITE Start to program or erase of Flash and data EEPROM. It is cleared automatically after 1 clock No operation...
  • Page 180 MC95FG0128A FEARL (Flash and EEPROM address low Register) : F2H ARL7 ARL6 ARL5 ARL4 ARL3 ARL2 ARL1 ARL0 Initial value : 00H ARL[7:0] Flash and EEPROM address low FEARM (Flash and EEPROM address middle Register) : F3H ARM7 ARM6 ARM5...

  • Page 181: Memory Map

    MC95FG0128A Program and erase time is controlled by setting FETCR register. Program and erase timer uses 10- bit counter. It increases by one at each divided system clock frequency(=SCLK/128). It is cleared when program or erase starts. Timer stops when 10-bit counter is same to FETCR. PEVBSY is cleared when program, erase or verify starts and set when program, erase or verify stops.

  • Page 182: Figure 15.2 Address Configuration Of Flash Memory

    MC95FG0128A PAGE ADDRESS WORD ADDRESS Program Memory 0x3FF Page 1023 0x7F Page 1022 0x00 Page 1 Page 0 * Page buffer size: 128Bytes 0x000 Figure 15.2 Address configuration of Flash memory 15.3.2 Data EEPROM Memory Map Data EEPROM memory uses 4K byte of EEPROM. It is read by byte and written by byte or page.

  • Page 183: Figure 15.4 Address Configuration Of Data Eeprom

    MC95FG0128A PAGE ADDRESS WORD ADDRESS Data Memory 0xFF Page 255 Page 254 Page 1 *Page buffer size: 16Bytes Page 0 0x00 Figure 15.4 Address configuration of data EEPROM Aug 02, 2018 Ver.2.9...

  • Page 184: Serial In-System Program Mode

    MC95FG0128A 15.4 Serial In-System Program Mode Serial in-system program uses the interface of debugger which uses two wires. Refer to chapter 14 in details about debugger 15.4.1 Flash operation Configuration(This Configuration is just used for follow description) FEMR[4] & [1] FEMR[5] &...

  • Page 185: Figure 15.6 The Sequence Of Bulk Erase Of Flash Memory

    MC95FG0128A Master Reset Page Buffer Reset Page Buffer Load Configuration Reg.<0> Set Erase Erase Latency(500us) Page Buffer Reset Configuration Reg.<0> clear Reg.<6:5> setting Cell Read Pass/Fail? Figure 15.6 The sequence of bulk erase of Flash memory 15.4.1.1 Flash Read Step 1. Enter OCD(=ISP) mode.
  • Page 186 MC95FG0128A (1) Write 0xAA to 0xF555. (2) Write 0x55 to 0xFAAA. (3) Write 0xA5 to 0xF555. Refer to how to enter ISP mode.. Command sequence to activate Flash write/erase mode. It is composed of sequentially writing data of Flash memory.
  • Page 187 MC95FG0128A (Only main cell area is erased. For bulk erase including OTP area, select OTP area.(set FEMR to 1000_1101.) Step 6. Set FETCR Step 7. Start bulk erase. FECR:1000_1011 Step 8. Insert one NOP operation Step 9. Read FESR until PEVBSY is 1.
  • Page 188 MC95FG0128A 15.4.1.9 Flash program verify mode Step 1. Enable program mode. Step 2. Set program verify mode. FEMR:1010_0011 Step 3. Read data from Flash. 15.4.1.10 OTP program verify mode Step 1. Enable program mode. Step 2. Set program verify mode. FEMR:1010_0111 Step 3.
  • Page 189 MC95FG0128A (1) Write 0xA5 to FEDR. (2) Write 0x5A to FEDR. Refer to how to enter ISP mode.. Command sequence to activate data EEPROM write/erase mode. It is composed of sequentially writing to data register(FEDR) 15.4.2.3 EEPROM write mode Step 1. Enable program mode.
  • Page 190 MC95FG0128A Step 7. Start bulk erase. FECR:0100_1011 Step 8. Insert one NOP operation Step 9. Read FESR until PEVBSY is 1. 15.4.2.6 Data EEPROM program verify mode Step 1. Enable program mode. Step 2. Set program verify mode. FEMR:0110_0011 Step 3. Read data from Flash.

  • Page 191: Parallel Mode

    MC95FG0128A 15.5 Parallel Mode 15.5.1 Overview Parallel program mode transfers address and data by byte. 3-byte address can be entered by one from the lease significant byte of address. If only LSB is changed, only one byte can be transferred.

  • Page 192: Figure 15.8 Parallel Byte Read Timing Of Program Memory

    MC95FG0128A PDATA ADDRL ADDRM ADDRH DATA0 DATA1 DATAn nALE n-byte data read with 2-byte address PDATA ADDRL ADDRM DATA0 DATA1 DATA2 DATAn nALE n-byte data write with 2-byte address PDATA ADDRL ADDRM DATA0 DATA1 DATA2 DATAn nALE n-byte data read...

  • Page 193: Figure 15.9 Parallel Byte Write Timing Of Program Memory

    MC95FG0128A 1 - byte write with 3 - byte address 1 - byte write with 2 - byte address 2 - byte write with 1 - byte address Write Write Write Write Write Write Write Write Read Write Data Data...

  • Page 194: Mode Entrance Method Of Isp And Byte-Parallel Mode

    MC95FG0128A 15.6 Mode entrance method of ISP and byte-parallel mode 15.6.1 Mode entrance method for ISP TARGET MODE DSDA DSCL DSDA ‘hC ‘hC ‘hC OCD(ISP) Release from worst 1.7V Power on reset Low period required during more 10us nTEST DSCL...

  • Page 195: Security

    MC95FG0128A 15.7 Security MC95FG0128A provides two Lock bits which can be left un-programmed (“0”) or can be programmed (“1”) to obtain the additional features listed in Table 15-5. The Lock bit can only be erased to “0” with the bulk erase command and a value of more than 0x80 at FETCR.
  • Page 196 MC95FG0128A 16. Configure option 16.1 Configure option Control Register FUSE_CONF (Pseudo-Configure Data) : 2F5DH SXINEN XINENA OCDSEL LOCKE LOCKF Initial value : 00H SXINEN Enable External Sub Oscillator Sub OSC disable (default) Sub OSC enable XINENA Enable External Main Oscillator...
  • Page 197 MC95FG0128A 17. APPENDIX A. Instruction Table Instructions are either 1, 2 or 3 bytes long as listed in the ‘Bytes’ column below. Each instruction takes either 1, 2 or 4 machine cycles to execute as listed in the following table. 1 machine cycle comprises 2 system clock cycles.
  • Page 198 MC95FG0128A XRL A,dir Exclusive-OR direct byte to A XRL A, @Ri Exclusive-OR indirect memory to A 66-67 XRL A,#data Exclusive-OR immediate to A XRL dir,A Exclusive-OR A to direct byte XRL dir,#data Exclusive-OR immediate to direct byte CLR A Clear A...
  • Page 199 MC95FG0128A CPL C Complement carry CPL bit Complement direct bit ANL C,bit AND direct bit to carry ANL C,/bit AND direct bit inverse to carry ORL C,bit OR direct bit to carry ORL C,/bit OR direct bit inverse to carry...
  • Page 200 MC95FG0128A B. Package relation MC95FG0128A MC95FG8128A MC95FG6128A Pin count Max I/O  Difference P6[4:7] (EC4,5)*  (removed functions P7[0:7] (PCI7) on standard P8[2:7] P8[0:7] MC95FG0128A) P9[0:7] (usart3) P9[0:7] (usart3) PA[0:5] PA[0:5] Notice *) Timer4,5 can not only use External clock input source mode.
  • Page 201 MC95FG0128A zzz: 080.0, xxx ; it possible to be error SETB 088.0 SJMP xxx: 088.0 while(1){ if (P00==1){ P10=1; } yyy: C,088.1 else { P10=0; } P11^=1; 088.1,C SJMP R7, #000 080.0, xxx ; it possible to be error unsigned char ret_bit_err(void) R7, #001 return !P00;...

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