Abov MC96F8204 Series User Manual

Abov MC96F8204 Series User Manual

Cmos single-chip 8-bit mcu with 12-bit a/d converter
Table of Contents

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CMOS single-chip 8-bit MCU
with 12-bit A/D converter
Main features
8-bit Microcontroller With High Speed 8051 CPU
Basic MCU Function
– 4Kbytes Flash Code Memory
– 256bytes IRAM
Built-in Analog Function
– Power-On Reset and Low Voltage Detect Reset
– Internal 8MHz RC Oscillator (±2.0%, T
– Internal 200kHz RC Oscillator (±3.0%, T
– Watchdog Timer RC Oscillator (5kHz)
Peripheral Features
– 12-bit Analog to Digital Converter (8 inputs)
– USART(UART + SPI) 1set
– I2C 8-bit x 1-ch
– 16-bit CRC/Checksum Generator
I/O and Packages
– Up to 18 Programmable I/O lines with 20 pin package.
– 8 SOP, 10 SSOP, 16 SOPN, 20 SOP, 20 TSSOP
– Pb-free package
Operating Conditions
– 1.8V to 5.5V Wide Voltage Range
– -40°C to 85°C Temperature Range
Application
– Small Home Appliance
= 0 ~ +50°C)
A
= -20 ~ +85°C)
A
MC96F8204
User's manual
V 1.4
Revised 21 December, 2016

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Summary of Contents for Abov MC96F8204 Series

  • Page 1 CMOS single-chip 8-bit MCU with 12-bit A/D converter MC96F8204 Main features User’s manual 8-bit Microcontroller With High Speed 8051 CPU  Basic MCU Function  V 1.4 – 4Kbytes Flash Code Memory – 256bytes IRAM Built-in Analog Function  – Power-On Reset and Low Voltage Detect Reset –...
  • Page 2: Revision History

    The information, diagrams and other data in this manual are correct and reliable; however, ABOV Semiconductor is in no way responsible for any violations of patents or other rights of the third party generated by the use of this manual.
  • Page 3: Overview

    MC96F8204 ABOV Semiconductor Co., Ltd. Overview 1.1. Description The MC96F8204 is advanced CMOS 8-bit microcontroller with 4 Kbytes of FLASH. This is powerful microcontroller which provides a highly flexible and cost effective solution to many embedded control applications. This provides the...
  • Page 4: Features

    MC96F8204 ABOV Semiconductor Co., Ltd. Features  – 8-bit CISC core (M8051, 2 clocks per cycle)  Interrupt Sources  ROM (FLASH) Capacity – External Interrupts – 4 Kbytes Flash with self read/write capability (EINT0/1/10/11/12) (5) – On Chip debug and In-System Programming(ISP) –...
  • Page 5: Development Tools

    1.3.2 OCD(On-chip debugger) emulator and debugger The OCD (On Chip Debug) emulator supports ABOV Semiconductor’s 8051 series MCU emulation. The OCD interface uses two-wire interfacing between PC and MCU which is attached to user’s system. The OCD can read or change the value of MCU internal memory and I/O peripherals. And the OCD also controls MCU internal debugging logic, it means OCD controls emulation, step run, monitoring, etc.
  • Page 6: Programmer

    MC96F8204 ABOV Semiconductor Co., Ltd. 1.3.3 Programmer Single programmer : E-PGM+ : It programs MCU device directly. DSDA DSCL Figure 1.2 E-PGM+ (Single writer)
  • Page 7 MC96F8204 ABOV Semiconductor Co., Ltd. OCD emulator: It can write code to MCU device too, because OCD debugger supports ISP (In System Programming).It does not require additional H/W, except developer’s target system. Gang programmer: E-GANG4 and E-GANG6 It can run PC controlled mode.
  • Page 8: Mtp Programming

    MC96F8204 ABOV Semiconductor Co., Ltd. MTP programming 1.4.1 Overview The program memory of MC96F8204 is MTP Type. This flash is accessed by serial data format. There are four pins(DSCL, DSDA, VDD, VSS) for programming/reading the flash. During programming Main chip...
  • Page 9: Circuit Design Guide

    MC96F8204 ABOV Semiconductor Co., Ltd. 1.4.3 Circuit Design Guide At the FLASH programming, the programming tool needs 4 signal lines that are DSCL, DSDA, VDD, and VSS. When you design the PCB circuits, you should consider the usage of these signal lines for the on-board programming.
  • Page 10: Block Diagram

    MC96F8204 ABOV Semiconductor Co., Ltd. Block diagram Flash CORE IRAM M8051 256B On-chip debug In-system programming General purpose I/O Power control 18 ports normal I/O Power on reset Low voltage reset Low voltage indicator Power down mode Watchdog timer 1 channel, 8-bit...
  • Page 11: Pin Assignment

    MC96F8204 ABOV Semiconductor Co., Ltd. Pin assignment P07/AN7/SCK/XOUT/SXOUT P00/AN0/EINT0/TXD/MOSI/DSDA P06/AN6/SS/XIN/SXIN P01/AN1/EINT1/RXD/MISO/DSCL P05/AN5/AVREF/EC1/RESETB P02/AN2/EINT11/T1O/PWM1O P04/AN4/EINT10/EC2/SDA P03/AN3/EINT12/T2O/PWM2O/SCL P10/(SDA) P11/(SCL) P12/(TXD/MOSI) P13/(RXD/MISO) P14/(SCK) NOTE) On On-Chip Debugging, ISP uses P0[1:0] pin as DSCL, DSDA. Figure 3.1 MC96F8204D 20SOP/TSSOP Pin Assignment P07/AN7/SCK/XOUT/SXOUT P00/AN0/EINT0/TXD/MOSI/DSDA P06/AN6/SS/XIN/SXIN...
  • Page 12 MC96F8204 ABOV Semiconductor Co., Ltd. P05/AN5/AVREF/EC1/RESETB P02/AN2/EINT11/T1O/PWM1O P04/AN4/EINT10/EC2/SDA P03/AN3/EINT12/T2O/PWM2O/SCL P06/AN6/SS/XIN/SXIN P01/AN1/EINT1/RXD/MISO/DSCL P07/AN7/SCK/XOUT/SXOUT P00/AN0/EINT0/TXD/MOSI/DSDA NOTE) On On-Chip Debugging, ISP uses P0[1:0] pin as DSCL, DSDA. The P10-P17 and P20-P21 pins should be selected as a push-pull output or an input with pull-up resistor by software control when the 10-pin package is used.
  • Page 13: Package Diagram

    MC96F8204 ABOV Semiconductor Co., Ltd. Package Diagram Figure 4.1 20-Pin SOP Package...
  • Page 14 MC96F8204 ABOV Semiconductor Co., Ltd. Figure 4.2 20-Pin TSSOP Package...
  • Page 15 MC96F8204 ABOV Semiconductor Co., Ltd. Figure 4.3 16-Pin SOPN Package...
  • Page 16 MC96F8204 ABOV Semiconductor Co., Ltd. Figure 4.4 10-Pin SSOP Package...
  • Page 17 MC96F8204 ABOV Semiconductor Co., Ltd. Figure 4.5 8-Pin SOP Package...
  • Page 18: Pin Description

    MC96F8204 ABOV Semiconductor Co., Ltd. Pin Description Function @RESET Shared with Name AN0/EINT0/TXD/MOSI/DSDA AN1/EINT1/RXD/MISO/DSCL AN2/EINT11/T1O/PWM1O Port 0 is a bit-programmable I/O port which can be configured as a schmitt-trigger input, a push-pull AN3/EINT12/T2O/PWM2O/SCL output, or an open-drain output. Input AN4/EINT10/EC2/SDA A pull-up resistor can be specified in 1-bit unit.
  • Page 19 MC96F8204 ABOV Semiconductor Co., Ltd. Function @RESET Shared with Name AVREF A/D converter reference voltage Input P05/AN5/EC1/RESETB P00/EINT0/TXD/MOSI/DSDA P01/EINT1/RXD/MISO/DSCL P02/EINT11/T1O/PWM1O P03/EINT12/T2O/PWM2O/SCL A/D converter analog input channels Input P04/EINT10/EC2/SDA P05/AVREF/EC1/RESETB P06/SS/XIN/SXIN P07/SCK/XOUT/SXOUT System reset pin with a pull-up resistor when it is...
  • Page 20: Port Structures

    MC96F8204 ABOV Semiconductor Co., Ltd. Port Structures General Purpose I/O Port Level Shift (VDC to ExtVDD) Level Shift (ExtVDD to VDC) PULL-UP REGISTER OPEN DRAIN REGISTER DATA REGISTER SUB-FUNC DATA OUTPUT SUB-FUNC ENABLE SUB-FUNC DIRECTION DIRECTION REGISTER CMOS or Schmitt Level...
  • Page 21: External Interrupt I/O Port

    MC96F8204 ABOV Semiconductor Co., Ltd. External Interrupt I/O Port Level Shift (VDC to ExtVDD) Level Shift (ExtVDD to VDC) PULL-UP REGISTER OPEN DRAIN REGISTER DATA REGISTER SUB-FUNC DATA OUTPUT SUB-FUNC ENABLE SUB-FUNC DIRECTION DIRECTION REGISTER EXTERNAL INTERRUPT POLARITY REG. INTERRUPT...
  • Page 22: Electrical Characteristics

    MC96F8204 ABOV Semiconductor Co., Ltd. Electrical Characteristics Absolute Maximum Ratings Parameter Symbol Rating Unit Note – Supply Voltage -0.3 ~ +6.5 -0.3 ~ VDD+0.3 Voltage on any pin with respect to VSS -0.3 ~ VDD+0.3 Maximum current output sourced by (I...
  • Page 23: A/D Converter Characteristics

    MC96F8204 ABOV Semiconductor Co., Ltd. A/D Converter Characteristics =-40°C ~ +85°C, VDD=1.8V ~ 5.5V, VSS=0V) Parameter Symbol Conditions Unit – – – – Resolution – – Integral Linear Error ±6 – – Differential Linearity Error ±1 AVREF= 2.7V – 5.5V fx= 8MHz –...
  • Page 24: Low Voltage Reset And Low Voltage Indicator Characteristics

    MC96F8204 ABOV Semiconductor Co., Ltd. Low Voltage Reset and Low Voltage Indicator Characteristics =-40°C ~ +85°C, VDD=1.8V ~ 5.5V, VSS=0V) Parameter Symbol Conditions Unit – 1.60 1.79 1.90 2.05 2.20 2.00 2.15 2.30 2.10 2.25 2.40 2.22 2.37 2.52 2.35 2.50...
  • Page 25: High Frequency Internal Rc Oscillator Characteristics

    MC96F8204 ABOV Semiconductor Co., Ltd. High Frequency Internal RC Oscillator Characteristics =-40°C ~ +85°C, VDD=1.8V ~ 5.5V, VSS=0V) Parameter Symbol Conditions Unit – – – Frequency HFIRC = 0°C to +50°C ±2.0 – – – Tolerance = -20°C to +85°C ±3.0...
  • Page 26: Dc Characteristics

    MC96F8204 ABOV Semiconductor Co., Ltd. DC Characteristics = -40°C ~ +85°C, VDD= 1.8V ~ 5.5V, VSS= 0V, f = 12MHz) Parameter Symbol Conditions Unit – Input High Voltage P0, P1, P2, RESETB 0.8VDD – – Input Low Voltage P0, P1, P2, RESETB 0.2VDD...
  • Page 27: Ac Characteristics

    MC96F8204 ABOV Semiconductor Co., Ltd. 7.10 AC Characteristics = -40°C ~ +85°C, VDD= 1.8V ~ 5.5V) Parameter Symbol Conditions Unit – – RESETB input low width VDD= 5V – – Interrupt input high, low width All interrupt, VDD= 5V External Counter Input High, ECWH –...
  • Page 28: Spi Characteristics

    MC96F8204 ABOV Semiconductor Co., Ltd. 7.11 SPI Characteristics =-40°C– +85°C, VDD=1.8V – 5.5V) Parameter Symbol Conditions Unit – – Output Clock Pulse Period Internal SCK source – – Input Clock Pulse Period External SCK source – – Output Clock High, Low Pulse Width...
  • Page 29: Uart Characteristics

    MC96F8204 ABOV Semiconductor Co., Ltd. 7.12 UART Characteristics =-40°C ~ +85°C, VDD=1.8V ~ 5.5V, f =11.1MHz) Parameter Symbol Unit Serial port clock cycle time 1250 x 16 1650 – Output data setup to clock rising edge x 13 – –...
  • Page 30: I2C Characteristics

    MC96F8204 ABOV Semiconductor Co., Ltd. 7.13 I2C Characteristics =-40°C ~ +85°C, VDD=1.8V ~ 5.5V) Standard Mode High-Speed Mode Parameter Symbol Unit Clock frequency – – Clock High Pulse Width SCLH – – Clock Low Pulse Width SCLL – – Bus Free Time –...
  • Page 31: Data Retention Voltage In Stop Mode

    MC96F8204 ABOV Semiconductor Co., Ltd. 7.14 Data Retention Voltage in Stop Mode =-40°C ~ +85°C, VDD=1.8V ~ 5.5V) Parameter Symbol Conditions Unit – – Data retention supply voltage DDDR VDDR= 1.8V, (T = 25°C), – – Data retention supply current...
  • Page 32: Internal Flash Rom Characteristics

    MC96F8204 ABOV Semiconductor Co., Ltd. 7.15 Internal Flash Rom Characteristics =-40°C ~ +85°C, VDD=1.8V ~ 5.5V, VSS= 0V) Parameter Symbol Condition Unit – – Sector Write Time – – Sector Erase Time – – Code Write Protection Time – –...
  • Page 33: Main Clock Oscillator Characteristics

    MC96F8204 ABOV Semiconductor Co., Ltd. 7.17 Main Clock Oscillator Characteristics =-40°C ~ +85°C, VDD=1.8V ~ 5.5V) Oscillator Parameter Condition Unit 2.0V – 5.5V – Crystal Main oscillation frequency 2.7V – 5.5V – 12.0 1.8V – 5.5V – Ceramic Oscillator Main oscillation frequency 2.7V –...
  • Page 34: Sub Clock Oscillator Characteristics

    MC96F8204 ABOV Semiconductor Co., Ltd. 7.18 Sub Clock Oscillator Characteristics = -40°C ~ +85°C, VDD = 2.2V ~ 5.5V) Oscillator Parameter Condition Unit Crystal Sub oscillation frequency 32.768 1.8V – 5.5V – External Clock SXIN input frequency Sub Clock Oscillator Characteristics Table 7.18...
  • Page 35: Main Oscillation Stabilization Characteristics

    MC96F8204 ABOV Semiconductor Co., Ltd. 7.19 Main Oscillation Stabilization Characteristics =-40°C ~ +85°C, VDD=1.8V ~ 5.5V) Oscillator Parameter Unit fx > 1MHz, VDD = 2.0V~5.5V – – Crystal Oscillation stabilization occurs when VDD is equal to the minimum oscillator voltage range.
  • Page 36: Operating Voltage Range

    MC96F8204 ABOV Semiconductor Co., Ltd. 7.21 Operating Voltage Range =0.4 to 12MHz)(Ceramic) =0.4 to 12MHz)(Crystal) 12.0MHz 12.0MHz 4.2MHz 4.2MHz 0.4MHz 0.4MHz Supply voltage (V) Supply voltage (V) Figure 7.14 Operating Voltage Range (Main OSC) =32 to 38kHz) 32.768kHz Supply voltage (V) Figure 7.15...
  • Page 37: Recommended Circuit And Layout

    MC96F8204 ABOV Semiconductor Co., Ltd. 7.22 Recommended Circuit and Layout This 0.1uF capacitor should be within 1cm from the VDD pin of MCU on the VDD VCC PCB layout. DC Power 0.1uF 0.1uF The MCU power line (VDD and VSS)
  • Page 38: Recommended Circuit And Layout With Smps Power

    MC96F8204 ABOV Semiconductor Co., Ltd. 7.23 Recommended Circuit and Layout with SMPS Power SMPS Side MCU Side SMPS 1. The C1 capacitor is to flatten out the voltage of the SMPS power, VCC. √ Recommended C1: 470uF/25V more. 2. The R1 and C2 are the RC filter for VDD and suppress the ripple of VCC.
  • Page 39: Typical Characteristics

    MC96F8204 ABOV Semiconductor Co., Ltd. 7.24 Typical Characteristics These graphs and tables provided in this section are only for design guidance and are not tested or guaranteed. In graphs or tables some data are out of specified operating range (e.g. out of specified VDD range). This is only for information and devices are guaranteed to operate properly only within the specified range.
  • Page 40: Table Of Contents

    MC96F8204 ABOV Semiconductor Co., Ltd. 1.60 1.40 1.20 X-tal 12MHz -40℃ 1.00 X-tal 12MHz +25℃ X-tal 12MHz +85℃ 0.80 HFIRC 8MHz -40℃ 0.60 HFIRC 8MHz +25℃ 0.40 HFIRC 8MHz +85℃ 0.20 0.00 2.5V 3.0V 3.5V 4.0V 4.5V 5.0V 5.5V Figure 7.21 X-TAL, HFIRC IDLE (IDD2) Current 100.0...
  • Page 41 MC96F8204 ABOV Semiconductor Co., Ltd. 140.0 120.0 100.0 -40℃ 80.0 +25℃ 60.0 +85℃ 40.0 20.0 2.5V 3.0V 3.5V 4.0V 4.5V 5.0V 5.5V Figure 7.23 SUB RUN (IDD3) Current 25.0 20.0 15.0 -40℃ +25℃ 10.0 +85℃ 2.5V 3.0V 3.5V 4.0V 4.5V 5.0V...
  • Page 42 MC96F8204 ABOV Semiconductor Co., Ltd. -40℃ +25℃ +85℃ 2.5V 3.0V 3.5V 4.0V 4.5V 5.0V 5.5V Figure 7.25 STOP (IDD5) Current...
  • Page 43: Memory

    MC96F8204 ABOV Semiconductor Co., Ltd. Memory The MC96F8204 addresses two separate address memory stores: Program memory and Data memory. The logical separation of Program and Data memory allows Data memory to be accessed by 8-bit addresses, which makes the 8- bit CPU access the data memory more rapidly.
  • Page 44 MC96F8204 ABOV Semiconductor Co., Ltd. FFFFH 0FFFH 4Kbytes 0000H Figure 8.1 Program Memory NOTE) 4 Kbytes Including Interrupt Vector Region...
  • Page 45: Data Memory

    MC96F8204 ABOV Semiconductor Co., Ltd. Data Memory Upper 128bytes Special Function Registers Internal RAM 128bytes (Indirect Addressing) (Direct Addressing) Lower 128bytes Internal RAM (Direct or Indirect Addressing) Figure 8.2 Data Memory Map The internal data memory space is divided into three blocks, which are generally referred to as the lower 128 bytes, upper 128 bytes, and SFR space.
  • Page 46 MC96F8204 ABOV Semiconductor Co., Ltd. 7F 7E 7D 7C 7B 7A 79 78 77 76 75 74 73 72 71 70 6F 6E 6D 6C 6B 6A 69 68 67 66 65 64 63 62 61 60 5F 5E 5D 5C 5B 5A 59 58...
  • Page 47: Extended Sfr Area

    MC96F8204 ABOV Semiconductor Co., Ltd. Extended SFR Area This area has no relation with RAM/FLASH. It can be read and written to through SFR with 8-bit unit. 505FH Extended Special Function Register (Indirect Addressing) 5050H Not used 0000H Figure 8.4...
  • Page 48: Sfr Map

    MC96F8204 ABOV Semiconductor Co., Ltd. SFR Map 8.4.1 SFR Map Summary Reserved M8051 compatible 00H/8H 01H/9H 02H/0AH 03H/0BH 04H/0CH 05H/0DH 06H/0EH 07H/0FH – – 0F8H FSADRH FSADRM FSADRL FIDR FMCR – – – – – – 0F0H I2CSAR1 0E8H RSTFR...
  • Page 49: Extended Sfr Map Summary

    MC96F8204 ABOV Semiconductor Co., Ltd. 8.4.2 Extended SFR Map Summary – Reserved 00H/8H 01H/9H 02H/0AH 03H/0BH 04H/0CH 05H/0DH 06H/0EH 07H/0FH – – – – – – – 5058H FCDRL 5050H FCSARH FCEARH FCSARM FCEARM FCSARL FCEARL FCCR FCDRH Table 8.2...
  • Page 50: Sfr Map

    MC96F8204 ABOV Semiconductor Co., Ltd. 8.4.3 SFR Map @Reset Address Function Symbol P0 Data Register Stack Pointer Data Pointer Register Low Data Pointer Register High Data Pointer Register Low 1 DPL1 Data Pointer Register High 1 DPH1 – – Low Voltage Indicator Control Register LVICR –...
  • Page 51: X-Tal

    MC96F8204 ABOV Semiconductor Co., Ltd. @Reset Address Function Symbol A/D Converter Control Low Register ADCCRL – – – A/D Converter Control High Register ADCCRH – – – – Extended Operation Register – – – Reserved – – – – External Interrupt Polarity 0 Register EIPOL0 –...
  • Page 52: Lfirc

    MC96F8204 ABOV Semiconductor Co., Ltd. @Reset Address Function Symbol – External Interrupt Flag Register EIFLAG – – – Reserved – – – Reserved – – – Reserved – – – – – – P2 Data Register – – – –...
  • Page 53 MC96F8204 ABOV Semiconductor Co., Ltd. @Reset Address Function Symbol Accumulator Register – – – Reserved – – – Reserved – – – Reserved – – – Reserved – – – Reserved – – – Reserved – – – Reserved –...
  • Page 54: Extended Sfr Map

    MC96F8204 ABOV Semiconductor Co., Ltd. 8.4.4 Extended SFR Map @Reset Address Function Symbol – – – – – – – 5050H Flash CRC Start Address High Register FCSARH – – – – – – – Flash CRC End Address High Register...
  • Page 55: Sfr Map

    MC96F8204 ABOV Semiconductor Co., Ltd. 8.4.5 SFR Map ACC (Accumulator Register) : E0H Initial value : 00H Accumulator B (B Register) : F0H Initial value : 00H B Register SP (Stack Pointer) : 81H Initial value : 07H Stack Pointer...
  • Page 56 MC96F8204 ABOV Semiconductor Co., Ltd. DPL1 (Data Pointer Register Low 1) : 84H DPL1 Initial value : 00H DPL1 Data Pointer Low 1 DPH1 (Data Pointer Register High 1) : 85H DPH1 Initial value : 00H DPH1 Data Pointer High 1...
  • Page 57: O Ports

    MC96F8204 ABOV Semiconductor Co., Ltd. I/O Ports I/O Ports The MC96F8204 has three groups of I/O ports (P0~P2). Each can be easily configured by software as I/O pin, internal pull up and open-drain pin to meet various system configurations and design requirements. Also P0 include function that can generate interrupt according to change of state of the pin.
  • Page 58: Register Map

    MC96F8204 ABOV Semiconductor Co., Ltd. 9.2.7 Register Map Name Address Direction Default Description P0 Data Register P0IO P0 Direction Register P0OD P0 Open-drain Selection Register P0PU P0 Pull-up Resistor Selection Register P0DB P0 Debounce Enable Register P0FSRH P0 Function Selection High Register...
  • Page 59: P0 Port

    MC96F8204 ABOV Semiconductor Co., Ltd. P0 Port 9.3.1 P0 Port Description P0 is 8-bit I/O port. P0 control registers consist of P0 data register (P0), P0 direction register (P0IO), debounce enable register (P0DB), P0 pull-up resistor selection register (P0PU), and P0 open-drain selection register (P0OD). Refer to the port function selection registers for the P0 function selection.
  • Page 60 MC96F8204 ABOV Semiconductor Co., Ltd. P0DB (P0 Debounce Enable Register) : 95H – DBCLK1 DBCLK0 P04DB P03DB P02DB P01DB P00DB – Initial value : 00H DBCLK[1:0] Configure Debounce Clock of Port DBCLK1 DBCLK0 Description fx/1 fx/4 fx/32 fx/4096 P04DB Configure Debounce of P04 Port...
  • Page 61 MC96F8204 ABOV Semiconductor Co., Ltd. P0FSRH (Port 0 Function Selection High Register) : 97H – – – P0FSRH4 P0FSRH3 P0FSRH2 P0FSRH1 P0FSRH0 – – – Initial value : 00H P0FSRH[4:2] P07 Function select P0FSRH4 P0FSRH3 P0FSRH2 Description I/O Port AN7 Function...
  • Page 62 MC96F8204 ABOV Semiconductor Co., Ltd. P0FSRM (Port 0 Function Selection Mid Register) : 8FH – – – – P0FSRM3 P0FSRM2 P0FSRM1 P0FSRM0 – – – – Initial value : 00H P0FSRM[3:2] P05 Function select P0FSRM3 P0FSRM2 Description I/O Port (EC1 function possible when input)
  • Page 63 MC96F8204 ABOV Semiconductor Co., Ltd. P0FSRL (Port 0 Function Selection Low Register) : 96H P0FSRL7 P0FSRL6 P0FSRL5 P0FSRL4 P0FSRL3 P0FSRL2 P0FSRL1 P0FSRL0 Initial value : 00H P0FSRL[7:6] P03 Function select P0FSRL7 P0FSRL6 Description I/O Port EINT12 function possible when input)
  • Page 64: P1 Port

    MC96F8204 ABOV Semiconductor Co., Ltd. P1 Port 9.4.1 P1 Port Description P1 is 8-bit I/O port. P1 control registers consist of P1 data register (P1), P1 direction register (P1IO), P1 pull-up resistor selection register (P1PU), and P1 open-drain selection register (P1OD). Refer to the port function selection registers for the P1 function selection.
  • Page 65 MC96F8204 ABOV Semiconductor Co., Ltd. P1FSR (Port 1 Function Selection Register) : A7H – – – P1FSR4 P1FSR3 P1FSR2 P1FSR1 P1FSR0 – – – Initial value : 00H P1FSR4 P14 Function select I/O Port SCK Function P1FSR3 P13 Function select...
  • Page 66: P2 Port

    MC96F8204 ABOV Semiconductor Co., Ltd. P2 Port 9.5.1 P2 Port Description P2 is 2-bit I/O port. P2 control registers consist of P2 data register (P2), P2 direction register (P2IO), P2 pull-up resistor selection register (P2PU), and P2 open-drain selection register (P2OD). Refer to the port function selection registers for the P2 function selection.
  • Page 67: Interrupt Controller

    MC96F8204 ABOV Semiconductor Co., Ltd. Interrupt Controller 10.1 Overview The MC96F8204 supports up to 15 interrupt sources. The interrupts have separate enable register bits associated with them, allowing software control. They can also have four levels of priority assigned to them. The non-maskable interrupt source is always enabled with a higher priority than any other interrupt source, and is not controllable by software.
  • Page 68 MC96F8204 ABOV Semiconductor Co., Ltd. Interrupt Highest Lowest Group 0 (Bit0) Interrupt 0 Interrupt 6 Interrupt 12 Interrupt 18 Highest 1 (Bit1) Interrupt 1 Interrupt 7 Interrupt 13 Interrupt 19 2 (Bit2) Interrupt 2 Interrupt 8 Interrupt 14 Interrupt 20...
  • Page 69: External Interrupt

    MC96F8204 ABOV Semiconductor Co., Ltd. 10.2 External Interrupt The external interrupt on INT0, INT1, INT10, INT11 and INT12 pins receive various interrupt request depending on the external interrupt polarity 0 register (EIPOL0) and external interrupt polarity 1 register (EIPOL1) as shown in Figure 10.1.
  • Page 70: Block Diagram

    MC96F8204 ABOV Semiconductor Co., Ltd. 10.3 Block Diagram EIPOL1 EIFLAG.2 EINT10 FLAG10 Priority High EIFLAG.3 EINT11 FLAG11 EIFLAG.4 EINT12 FLAG12 Reserved Reserved EIFLAG.0 EINT0 FLAG0 EIPOL0 Reserved I2CIFR Reserved USART Rx USART Tx EIFLAG.1 EINT1 FLAG1 Level 0 Level 1...
  • Page 71: Interrupt Vector Table

    MC96F8204 ABOV Semiconductor Co., Ltd. 10.4 Interrupt Vector Table The interrupt controller supports 24 interrupt sources as shown in the Table 10-2. When interrupt is served, long call instruction (LCALL) is executed and program counter jumps to the vector address. All interrupt requests have their own priority order.
  • Page 72: Interrupt Sequence

    MC96F8204 ABOV Semiconductor Co., Ltd. 10.5 Interrupt Sequence An interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to ‘0’ by a reset or an instruction. Interrupt acceptance always generates at last cycle of the instruction. So instead of fetching the current instruction, CPU executes internally LCALL instruction and saves the PC at stack.
  • Page 73: Effective Timing After Controlling Interrupt Bit

    MC96F8204 ABOV Semiconductor Co., Ltd. 10.6 Effective Timing after Controlling Interrupt Bit Case a) Control Interrupt Enable Register (IE, IE1, IE2, IE3) Interrupt Enable Register command After executing IE set/clear, enable register is effective. Next Instruction Next Instruction Figure 10.4...
  • Page 74: Multi Interrupt

    MC96F8204 ABOV Semiconductor Co., Ltd. 10.7 Multi Interrupt If two requests of different priority levels are received simultaneously, the request of higher priority level is served first. If more than one interrupt request are received, the interrupt polling sequence determines which request is served first by hardware.
  • Page 75: Interrupt Enable Accept Timing

    MC96F8204 ABOV Semiconductor Co., Ltd. 10.8 Interrupt Enable Accept Timing Max. 4 Machine Cycle 4 Machine Cycle System Clock Interrupt goes Active Interrupt Interrupt Processing Latched Interrupt Routine : LCALL & LJMP Figure 10.7 Interrupt Response Timing Diagram 10.9 Interrupt Service Routine Address...
  • Page 76: Interrupt Timing

    MC96F8204 ABOV Semiconductor Co., Ltd. 10.11 Interrupt Timing Interrupt sampled here CLP2 CLP1 CLP2 C1P1 C1P2 C2P1 C2P2 SCLK INT_SRC INTR_ACK LAST_CYC INTR_LCALL 8-Bit interrupt Vector INT_VEC {8’h00, INT_VEC} PROGA Figure 10.10 Timing Chart of Interrupt Acceptance and Interrupt Return Instruction Interrupt sources are sampled at the last cycle of a command.
  • Page 77: Interrupt Register Overview

    MC96F8204 ABOV Semiconductor Co., Ltd. 10.12 Interrupt Register Overview 10.12.1 Interrupt Enable Register (IE, IE1, IE2, IE3) Interrupt enable register consists of global interrupt control bit (EA) and peripheral interrupt control bits. Total 24 peripherals are able to control interrupt.
  • Page 78: Interrupt Register Description

    MC96F8204 ABOV Semiconductor Co., Ltd. 10.12.6 Interrupt Register Description The interrupt register is used for controlling interrupt functions. Also it has external interrupt control registers. The interrupt register consists of interrupt enable register (IE), interrupt enable register 1 (IE1), interrupt enable register 2 (IE2) and interrupt enable register 3 (IE3).
  • Page 79 MC96F8204 ABOV Semiconductor Co., Ltd. IE1 (Interrupt Enable Register 1): A9H – – – – INT11E INT10E INT9E INT7E – – – – Initial value: 00H INT11E Enable or Disable External interrupt 1 (EINT1) Disable Enable INT10E Enable or Disable USART Tx interrupt...
  • Page 80 MC96F8204 ABOV Semiconductor Co., Ltd. IE2 (Interrupt Enable Register 2) : AAH –- – – – – INT15E INT14E INT13E – – – – – Initial value : 00H INT15E Enable or Disable Timer 2 Match Interrupt Disable Enable INT14E...
  • Page 81 MC96F8204 ABOV Semiconductor Co., Ltd. IP (Interrupt Priority Register) : B8H – – – – Initial value : 00H IP1 (Interrupt Priority Register 1) : F8H – – IP15 IP14 IP13 IP12 IP11 IP10 – – Initial value : 00H...
  • Page 82 MC96F8204 ABOV Semiconductor Co., Ltd. EIFLAG (External Interrupt Flag 0 Register) : C0H – T0IFR IICIFR FLAG12 FLAG11 FLAG10 FLAG1 FLAG0 – Initial value : 00H When T0 interrupt occurs, this bit becomes ‘1’. For clearing bit, write ‘0’ to this bit or T0IFR auto clear by INT_ACK signal.
  • Page 83: Peripheral Hardware

    MC96F8204 ABOV Semiconductor Co., Ltd. Peripheral Hardware 11.1 Clock Generator 11.1.1 Overview As shown in Figure 11.1, the clock generator produces the basic clock pulses which provide the system clock to be supplied to the CPU and the peripheral hardware. It contains main/sub-frequency clock oscillator. The main/sub clock operation can be easily obtained by attaching a crystal between the XIN/SXIN and XOUT/SXOUT pin, respectively.
  • Page 84: Block Diagram

    MC96F8204 ABOV Semiconductor Co., Ltd. 11.1.2 Block Diagram XCLKE STOP Mode SCLK (fx) System (Core, System, Clock Gen. Peripheral) Main OSC XOUT STOP Mode LFIRCS[1:0] Stabilization Time LFIRCE Generation BITCK[1:0] LF INT-RC LFIRC overflow WDT clock (200kHz) fx/4096 Internal fx/1024...
  • Page 85: Register Map

    MC96F8204 ABOV Semiconductor Co., Ltd. 11.1.3 Register Map Name Address Direction Default Description SCCR System and Clock Control Register OSCCR Oscillator Control Register LIFSR LFIRC Frequency Selection Register XTFLSR X-tal Filter Selection Register Clock Generator Register Map Table 11.1 11.1.4 Clock Generator Register Description The clock generator register uses clock control for system operation.
  • Page 86 MC96F8204 ABOV Semiconductor Co., Ltd. OSCCR (Oscillator Control Register) : C8H – LFIRCE HFIRCS2 HFIRCS1 HFIRCS0 HFIRCE XCLKE SCLKE – Initial value : 08H LFIRCE Control the operation of the low frequency internal RC oscillator Disable operation of LF INT-RC OSC...
  • Page 87 MC96F8204 ABOV Semiconductor Co., Ltd. XTFLSR (X-tal Filter Selection Register): BFH WTP4 WTP3 WTP2 WTP1 WTP0 XRNS2 XRNS1 XRNS0 Initial value: 00H Write Identification bits. These bits are automatically cleared to “00000b” immediately WTP[4:0] after XTFLSR write. 0x00 on read.
  • Page 88: Basic Interval Timer

    MC96F8204 ABOV Semiconductor Co., Ltd. 11.2 Basic Interval Timer 11.2.1 Overview The MC96F8204 has one 8-bit basic interval timer that is free-run and can’t stop. Block diagram is shown in Figure 11.2. In addition, the basic interval timer generates the time base for watchdog timer counting. It also provides a basic interval timer interrupt (BITIFR).
  • Page 89: Basic Interval Timer Register Description

    MC96F8204 ABOV Semiconductor Co., Ltd. 11.2.4 Basic Interval Timer Register Description The basic interval timer register consists of basic interval timer counter register (BITCNT) and basic interval timer control register (BITCR). If BCLR bit is set to ‘1’, BITCNT becomes ‘0’ and then counts up. After 1 machine cycle, BCLR bit is cleared to ‘0’...
  • Page 90: Watch Dog Timer

    MC96F8204 ABOV Semiconductor Co., Ltd. 11.3 Watch Dog Timer 11.3.1 Overview The watchdog timer rapidly detects the CPU malfunction such as endless looping caused by noise or something like that, and resumes the CPU to the normal state. The watchdog timer signal for malfunction detection can be used as either a CPU reset or an interrupt request.
  • Page 91: Block Diagram

    MC96F8204 ABOV Semiconductor Co., Ltd. 11.3.3 Block Diagram clear WDT Clock To RESET WDTCNT Circuit WDTEN To interrupt WDTIFR block clear WDTDR INT_ACK WDTCL WDTRSON WDTCR Figure 11.4 Watch Dog Timer Block Diagram 11.3.4 Register Map Name Address Direction Default...
  • Page 92: Register Description For Watch Dog Timer

    MC96F8204 ABOV Semiconductor Co., Ltd. 11.3.6 Register Description for Watch Dog Timer WDTCNT (Watch Dog Timer Counter Register: Read Case) : 8EH WDTCNT 7 WDTCNT 6 WDTCNT 5 WDTCNT 4 WDTCNT3 WDTCNT 2 WDTCNT 1 WDTCNT 0 Initial value : 00H...
  • Page 93: Watch Timer

    MC96F8204 ABOV Semiconductor Co., Ltd. 11.4 Watch Timer 11.4.1 Overview The watch timer has the function for RTC (Real Time Clock) operation. It is generally used for RTC design. The internal structure of the watch timer consists of the clock source select circuit, timer counter circuit, output select circuit and watch timer control register.
  • Page 94: Register Map

    MC96F8204 ABOV Semiconductor Co., Ltd. 11.4.3 Register Map Name Address Direction Default Description WTCNT Watch Timer Counter Register WTDR Watch Timer Data Register WTCR Watch Timer Control Register Watch Timer Register Map Table 11.4 11.4.4 Watch Timer Register Description The watch timer register consists of watch timer counter register (WTCNT), watch timer data register (WTDR) and watch timer control register (WTCR).
  • Page 95 MC96F8204 ABOV Semiconductor Co., Ltd. WTCR (Watch Timer Control Register): 9EH – – WTEN WTIFR WTIN1 WTIN0 WTCK1 WTCK0 – – Initial value: 00H WTEN Control Watch Timer Disable Enable When WT Interrupt occurs, this bit becomes ‘1’. For clearing bit, write ‘0’ to this bit or WTIFR automatically clear by INT_ACK signal.
  • Page 96: Timer 0

    MC96F8204 ABOV Semiconductor Co., Ltd. 11.5 Timer 0 11.5.1 Overview The 8-bit timer 0 consists of multiplexer, timer 0 counter register, timer 0 data register, timer 0 capture data register and timer 0 control register (T0CNT, T0DR, T0CDR, T0CR). It has two operating modes: −...
  • Page 97: 8-Bit Timer/Counter Mode

    MC96F8204 ABOV Semiconductor Co., Ltd. 11.5.2 8-bit Timer/Counter Mode The 8-bit timer/counter mode is selected by control register as shown in Figure 11.5. The 8-bit timer have counter and data register. The counter register is increased by internal. Timer 0 can use the input clock with one of 2, 4, 8, 32, 128, 512 and 2048 prescaler division rates (T0CK[2:0]).
  • Page 98: 8-Bit Capture Mode

    MC96F8204 ABOV Semiconductor Co., Ltd. 11.5.3 8-bit Capture Mode The timer 0 capture mode is set by T0MS as ‘1’. The clock source can use the internal/external clock. Basically, it has the same function as the 8-bit timer/counter mode and the interrupt occurs when T0CNT is equal to T0DR. T0CNT value is automatically cleared by match signal and it can be also cleared by software (T0CC).
  • Page 99 MC96F8204 ABOV Semiconductor Co., Ltd. T0CDR Load T0CNT Value Count Pulse Period Up-count TIME Ext. EINT10 PIN Interrupt Request (FLAG10) Interrupt Interval Period Figure 11.9 Input Capture Mode Operation for Timer 0 T0CNT Interrupt Request (T0IFR) Ext. EINT10 PIN Interrupt...
  • Page 100: Block Diagram

    MC96F8204 ABOV Semiconductor Co., Ltd. 11.5.4 Block Diagram fx/2 fx/4 8-bit Timer 0 Counter fx/8 Clear T0CC fx/32 INT_ACK T0CNT (8Bit) Match signal fx/128 Clear fx/512 Clear Match To interrupt fx/2048 T0EN T0IFR block Comparator T0DR (8Bit) T0CK[2:0] 8-bit Timer 0 Data Register...
  • Page 101: Register Description For Timer/Counter 0

    MC96F8204 ABOV Semiconductor Co., Ltd. 11.5.7 Register Description for Timer/Counter 0 T0CNT (Timer 0 Counter Register) : 91H T0CNT7 T0CNT6 T0CNT5 T0CNT4 T0CNT3 T0CNT2 T0CNT1 T0CNT0 Initial value : 00H T0CNT[7:0] T0 Counter T0DR (Timer 0 Data Register) : 92H...
  • Page 102 MC96F8204 ABOV Semiconductor Co., Ltd. T0CR (Timer 0 Control Register) : 90H – – T0EN T0MS T0CK2 T0CK1 T0CK0 T0CC – – Initial value : 00H T0EN Control Timer 0 Timer 0 disable Timer 0 enable(Counter clear and start) T0MS...
  • Page 103: Timer 1/2

    MC96F8204 ABOV Semiconductor Co., Ltd. 11.6 Timer 1/2 11.6.1 Overview The 16-bit timer 1/2 consists of multiplexer, timer 1/2 A data register high/low, timer 1/2 B data register high/low and timer 1/2 control register high/low (TnADRH, TnADRL, TnBDRH, TnBDRL, TnCRH, TnCRL).
  • Page 104 MC96F8204 ABOV Semiconductor Co., Ltd. ADDRESS : 99H/B1H TnEN TnMS1 TnMS0 TnCC Tn CRH INITIAL VALUE : 0000_ 0000B ADDRESS : 98H/B0H TnCK2 TnCK1 TnCK0 TnIFR RLDnEN Tn POL Tn ECE Tn CNTR Tn CRL INITIAL VALUE : 0000_ 0000B...
  • Page 105: 16-Bit Capture Mode

    MC96F8204 ABOV Semiconductor Co., Ltd. 11.6.3 16-bit Capture Mode The 16-bit timer 1/2 capture mode is set by TnMS[1:0] as ‘01’. The clock source can use the internal/external clock. Basically, it has the same function as the 16-bit timer/counter mode and the interrupt occurs when TnCNTH/TnCNTL is equal to TnADRH/TnADRL.
  • Page 106 MC96F8204 ABOV Semiconductor Co., Ltd. TnBDRH/L Load TnCNTH/L Value Count Pulse Period Up-count TIME Ext. EINT1n PIN Interrupt Request (FLAG1n) Interrupt Interval Period Figure 11.15 Input Capture Mode Operation for Timer 1/2 FFFF FFFF TnCNTH/L Interrupt Request (TnIFR) Ext. EINT1n PIN...
  • Page 107: 16-Bit Ppg Mode

    MC96F8204 ABOV Semiconductor Co., Ltd. 11.6.4 16-bit PPG Mode The timer 1/2 has a PPG (Programmable Pulse Generation) function. In PPG mode, TnO/PWMnO pin outputs up to 16-bit resolution PWM output. This pin should be configured as a PWM output by setting P0FSRL[5:4](T1), P0FSRL[7:6](T2) to ‘01’.
  • Page 108 MC96F8204 ABOV Semiconductor Co., Ltd. Repeat Mode(TnMS = 11b) and "Start High"(TnPOLA = 0b). Clear and Start Set TnEN Timer n clock Counter TnADRH/L Tn Interrupt 1. TnBDRH/L(5) < TnADRH/L PWMnO B Match A Match 2. TnBDRH/L >= TnADRH/L PWMnO A Match 3.
  • Page 109: Block Diagram

    MC96F8204 ABOV Semiconductor Co., Ltd. 11.6.5 Block Diagram 16-bit A Data Register TnADRH/TnADRL A Match Reload TnCC TnEN RLDnEN TnECE TnCK[2:0] INT_ACK Buffer Register A To other block Clear Edge Detector A Match To interrupt TnIFR fx/1 TnEN block Comparator...
  • Page 110: Timer/Counter 1/2 Register Description

    MC96F8204 ABOV Semiconductor Co., Ltd. 11.6.7 Timer/Counter 1/2 Register Description The timer/counter 1/2 register consists of timer 1/2 A data high register (TnADRH), timer 1/2 A data low register (TnADRL), timer 1/2 B data high register (TnBDRH), timer 1/2 B data low register (TnBDRL), timer 1/2 control high register (TnCRH) and timer 1/2 control low register (TnCRL).
  • Page 111 MC96F8204 ABOV Semiconductor Co., Ltd. TnCRH (Timer n Control High Register) : 99H/B1H, Where n = 1 and 2 – – – – TnEN TnMS1 TnMS0 TnCC – – – – Initial value : 00H TnEN Control Timer n Timer n disable...
  • Page 112 MC96F8204 ABOV Semiconductor Co., Ltd. TnCRL (Timer n Control Low Register) : 98H/B0H, Where n = 1 and 2 TnCK2 TnCK1 TnCK0 TnIFR RLDnEN TnPOL TnECE TnCNTR Initial value : 00H TnCK[2:0] Select Timer n clock source. fx is main system clock frequency...
  • Page 113: 12-Bit A/D Converter

    MC96F8204 ABOV Semiconductor Co., Ltd. 11.7 12-bit A/D Converter 11.7.1 Overview The analog-to-digital converter (A/D) allows conversion of an analog input signal to corresponding 12-bit digital value. The A/D module has eight analog inputs. The output of the multiplexer is the input into the converter which generates the result through successive approximation.
  • Page 114: Block Diagram

    MC96F8204 ABOV Semiconductor Co., Ltd. 11.7.3 Block Diagram TRIG ADSEL[3:0] ADST Start (Select one input pin T1 A match signal of the assigned pins) Clock ADCLK Selector Clear AFLAG Input Pins Comparator Control To interrupt ADCIFR Logic block VDD19 Clear...
  • Page 115: Adc Operation

    MC96F8204 ABOV Semiconductor Co., Ltd. 11.7.4 ADC Operation Align bit set “0” ADCO11 ADCO10 ADCO9 ADCO8 ADCO7 ADCO6 ADCO5 ADCO4 ADCO3 ADCO2 ADCO1 ADCO0 ADCDRH7 ADCDRH6 ADCDRH5 ADCDRH4 ADCDRH3 ADCDRH2 ADCDRH1 ADCDRH0 ADCDRL7 ADCDRL6 ADCDRL5 ADCDRL4 ADCDRH[7:0] ADCDRL[7:4] ADCDRL[3:0] bits are “0”...
  • Page 116 MC96F8204 ABOV Semiconductor Co., Ltd. SET ADCCRH Select ADC Clock and Data Align Bit. SET ADCCRL ADC enable & Select AN Input Channel. Converting START Start ADC Conversion. If Conversion is completed, AFLAG is set “1” and ADC interrupt is AFLAG = 1? occurred.
  • Page 117: Register Map

    MC96F8204 ABOV Semiconductor Co., Ltd. 11.7.5 Register Map Name Address Direction Default Description ADCCRH A/D Converter Control High Register ADCCRL A/D Converter Control Low Register ADCDRH A/D Converter Data High Register ADCDRL A/D Converter Data Low Register ADC Register Map Table 11.9...
  • Page 118: Register Description For Adc

    MC96F8204 ABOV Semiconductor Co., Ltd. 11.7.7 Register Description for ADC ADCDRH (A/D Converter Data High Register) : CFH ADDM11 ADDM10 ADDM9 ADDM8 ADDM7 ADDM6 ADDM5 ADDM4 ADDL11 ADDL10 ADDL9 ADDL8 Initial value : xxH ADDM[11:4] MSB align, A/D Converter High Data (8-bit)
  • Page 119 MC96F8204 ABOV Semiconductor Co., Ltd. ADCCRH (A/D Converter Control High Register) : A1H – – – ADCIFR TRIG ALIGN CKSEL1 CKSEL0 – – – Initial value : 00H When ADC Interrupt occurs, this bit becomes ‘1’. For clearing bit, write ‘0’ to this bit or ADCIFR auto clear by INT_ACK signal.
  • Page 120 MC96F8204 ABOV Semiconductor Co., Ltd. ADCCRL (A/D Converter Control Low Register) : A0H STBY ADST REFSEL AFLAG ADSEL3 ADSEL2 ADSEL1 ADSEL0 Initial value : 00H STBY Control Operation of A/D (The ADC module is automatically disabled at stop mode) ADC module disable...
  • Page 121: Usart

    MC96F8204 ABOV Semiconductor Co., Ltd. 11.8 USART 11.8.1 Overview The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device. The main features are listed below. − Full Duplex Operation (Independent Serial Receive and Transmit Registers) −...
  • Page 122: Uart Block Diagram

    MC96F8204 ABOV Semiconductor Co., Ltd. 11.8.2 UART Block Diagram Master Control USTMS[1:0] SCLK USTBD (fx: System clock) To interrupt block Baud Rate Generator DBLS WAKEIE RXCIE Clock Sync Logic At Stop mode WAKE Low level detector Clock Recovery Control USTS[2:0]...
  • Page 123: Usart Clock Generation

    MC96F8204 ABOV Semiconductor Co., Ltd. 11.8.3 USART Clock Generation USTBD DBLSn SCLK (USTBD+1) Prescaling Up-Counter txclk SCLK MASTERn Edge Sync Register USTMS[1:0] Detector CPOL rxclk Figure 11.26 Clock Generation Block Diagram (USART) The clock generation logic generates the base clock for the transmitter and receiver. The USART supports four modes of clock operation and those are normal asynchronous, double speed asynchronous, master synchronous and slave synchronous mode.
  • Page 124: External Clock (Sck)

    MC96F8204 ABOV Semiconductor Co., Ltd. 11.8.4 External Clock (SCK) External clocking is used in the synchronous or SPI slave mode of operation. External clock input from the SCK pin is sampled by a synchronization logic to remove meta-stability. The output from the synchronization logic must be passed through an edge detector before it is used by the transmitter and receiver.
  • Page 125: Uart Data Format

    MC96F8204 ABOV Semiconductor Co., Ltd. 11.8.6 UART Data format A serial frame is defined to be one character of data bits with synchronization bits (start and stop bits), and optionally a parity bit for error detection. The USART supports all 30 combinations of the following as valid frame formats.
  • Page 126: Uart Parity Bit

    MC96F8204 ABOV Semiconductor Co., Ltd. 11.8.7 UART Parity bit The parity bit is calculated by doing an exclusive-OR of all the data bits. If odd parity is used, the result of the exclusive-OR is inverted. The parity bit is located between the MSB and first stop bit of a serial frame.
  • Page 127: Uart Parity Generator

    MC96F8204 ABOV Semiconductor Co., Ltd. UART Parity Generator 11.8.8.3 The parity generator calculates the parity bit for the serial frame data to be sent. When parity bit is enabled (USTP1=1), the transmitter control logic inserts the parity bit between the MSB and the first stop bit of the frame to be sent.
  • Page 128: Uart Receiver Flag And Interrupt

    MC96F8204 ABOV Semiconductor Co., Ltd. UART Receiver Flag and Interrupt 11.8.9.2 The UART receiver has one flag that indicates the receiver state. The receive complete (RXC) flag indicates whether there are unread data in the receive buffer. This flag is set when there is unread data in the receive buffer and cleared when the receive buffer is empty.
  • Page 129: Asynchronous Data Reception

    MC96F8204 ABOV Semiconductor Co., Ltd. Asynchronous Data Reception 11.8.9.5 To receive asynchronous data frame, the USART includes a clock and data recovery unit. Theclock recovery logic is used for synchronizing the internally generated baud-rate clock to the incoming asynchronous serial frame on the RXD pin.
  • Page 130 MC96F8204 ABOV Semiconductor Co., Ltd. When the receiver is enabled (RXE=1), the clock recovery logic tries to find a high-to-low transition on the RXD line, the start bit condition. After detecting high to low transition on RXD line, the clock recovery logic uses samples 8, 9 and 10 for normal mode to decide if a valid start bit is received.
  • Page 131: Spi Mode

    MC96F8204 ABOV Semiconductor Co., Ltd. 11.8.10 SPI Mode The USART can be set to operate in industrial standard SPI compliant mode. The SPI mode has the following features. − Full Duplex, Three-wire synchronous data transfer − Mater and Slave Operation −...
  • Page 132 MC96F8204 ABOV Semiconductor Co., Ltd. (CPOL=0) (CPOL=1) SAMPLE MOSI MSB First … BIT7 BIT6 BIT2 BIT1 BIT0 LSB First … BIT0 BIT1 BIT5 BIT6 BIT7 MISO /SS OUT (MASTER) /SS IN (SLAVE) Figure 11.32 USART SPI Clock Formats when CPHA=0 When CPHA=0, the slave begins to drive its MISO output with the first data bit value when SS goes to active low.
  • Page 133 MC96F8204 ABOV Semiconductor Co., Ltd. (CPOL=0) (CPOL=1) SAMPLE MOSI … MSB First BIT7 BIT6 BIT2 BIT1 BIT0 … LSB First BIT0 BIT1 BIT5 BIT6 BIT7 MISO /SS OUT (MASTER) /SS IN (SLAVE) Figure 11.33 USART SPI Clock Formats when CPHA=1 When CPHA=1, the slave begins to drive its MISO output when SS goes active low, but the data is not defined until the first SCK edge.
  • Page 134: Usart Spi Block Diagram

    MC96F8204 ABOV Semiconductor Co., Ltd. 11.8.12 USART SPI Block Diagram USTBD Control SCLK Baud Rate Generator (fx: System clock) MASTER USTSSEN Edge Detector Control Controller FXCH CPOL CPHA MISO Data Receive Shift Register Rx Control Recovery (RXSR) RXCIE DOR Checker...
  • Page 135: Register Map

    MC96F8204 ABOV Semiconductor Co., Ltd. 11.8.13 Register Map Name Address Direction Default Description USTCR1 USART Control Register 1 USTCR2 USART Control Register 2 USTCR3 USART Control Register 3 USTST USART Status Register USTBD USART Baud Rate Generation Register USTDR USART Data Register USART Register Map Table 11.12...
  • Page 136 MC96F8204 ABOV Semiconductor Co., Ltd. USTCR1 (USART Control Register 1) : D9H USTS1 USTS0 USTMS1 USTMS0 USTP1 USTP0 USTS2 CPOL CPHA Initial value : 00H USTMS [1:0] Selects Operation Mode of USART USTMS1 USTMS0 Operation mode Asynchronous Mode (UART) Synchronous Mode...
  • Page 137 MC96F8204 ABOV Semiconductor Co., Ltd. USTCR2 (USART Control Register 2) : DAH DRIE TXCIE RXCIE WAKEIE USTEN DBLS Initial value : 00H URIE Interrupt enable bit for Data Register Interrupt from DRE is inhibited (use polling) When DRE is set, request an interrupt...
  • Page 138 MC96F8204 ABOV Semiconductor Co., Ltd. USTCR3 (USART Control Register 3) : DBH MASTER LOOPS DISSCK USTSSEN FXCH USTSB USTTX8 USTRX8 Initial value : 00H MASTER Selects master or slave in SPI or Synchronous mode operation and controls the direction of SCK pin.
  • Page 139 MC96F8204 ABOV Semiconductor Co., Ltd. USTST (USART Status Register) : DCH WAKE USTRST Initial value : 80H The DRE flag indicates if the transmit buffer (USTDR) is ready to receive new data. If DRE is ‘1’, the buffer is empty and ready to be written. The flag can generate a DRE interrupt.
  • Page 140: Overview

    MC96F8204 ABOV Semiconductor Co., Ltd. 11.9 11.9.1 Overview The I2C is one of industrial standard serial communication protocols, and which uses 2 bus lines Serial Data Line (SDA) and Serial Clock Line (SCL) to exchange data. Because both SDA and SCL lines are open-drain output, each line needs pull-up resistor.
  • Page 141: I2C Bit Transfer

    MC96F8204 ABOV Semiconductor Co., Ltd. 11.9.3 I2C Bit Transfer The data on the SDA line must be stable during HIGH period of the clock, SCL. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW. The exceptions are START(S), repeated START(Sr) and STOP(P) condition where data line changes when clock line is high.
  • Page 142: Data Transfer

    MC96F8204 ABOV Semiconductor Co., Ltd. 11.9.5 Data Transfer Every byte put on the SDA line must be 8-bits long. The number of bytes that can be transmitted per transfer is unlimited. Each byte has to be followed by an acknowledge bit. Data is transferred with the most significant bit (MSB) first.
  • Page 143: I2C Acknowledge

    MC96F8204 ABOV Semiconductor Co., Ltd. 11.9.6 I2C Acknowledge The acknowledge related clock pulse is generated by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDA line during the acknowledge clock pulse so that it remains stable LOW during the HIGH period of this clock pulse.
  • Page 144: Synchronization / Arbitration

    MC96F8204 ABOV Semiconductor Co., Ltd. 11.9.7 Synchronization / Arbitration Clock synchronization is performed using the wired-AND connection of I2C interfaces to the SCL line. This means that a HIGH to LOW transition on the SCL line will cause the devices concerned to start counting off their LOW period and it will hold the SCL line in that state until the clock HIGH state is reached.
  • Page 145: Operation

    MC96F8204 ABOV Semiconductor Co., Ltd. 11.9.8 Operation The I2C is byte-oriented and interrupt based. Interrupts are issued after all bus events except for a transmission of a START condition. Because the I2C is interrupt based, the application software is free to carry on other operations during a I2C byte transfer.
  • Page 146 MC96F8204 ABOV Semiconductor Co., Ltd. 3) Master transmits repeated START condition with not checking ACK signal. In this case, load SLA+R/W into the I2CDR and set STARTC bit in I2CCR. After doing one of the actions above, clear to “0b” all interrupt source bits in I2CSR to release SCL line. In case of 1), move to step 7.
  • Page 147: Master Receiver

    MC96F8204 ABOV Semiconductor Co., Ltd. Master Receiver 11.9.8.2 To operate I2C in master receiver, follow the recommended steps below. Enable I2C by setting IICEN bit in I2CCR. This provides main clock to the peripheral. Load SLA+R into the I2CDR where SLA is address of slave device and R is transfer direction from the viewpoint of the master.
  • Page 148 MC96F8204 ABOV Semiconductor Co., Ltd. I2C can choose one of the following cases according to the RXACK flag in I2CSR. 1) Master continues receiving data from slave. To do this, set ACKEN bit in I2CCR to Acknowledge the next data to be received.
  • Page 149: I2C Slave Transmitter

    MC96F8204 ABOV Semiconductor Co., Ltd. I2C Slave Transmitter 11.9.8.3 To operate I2C in slave transmitter, follow the recommended steps below. If the main operating clock (SCLK) of the system is slower than that of SCL, load value 0x00 into I2CSDHR to make SDA change within one system clock period from the falling edge of SCL.
  • Page 150: Slave Receiver

    MC96F8204 ABOV Semiconductor Co., Ltd. Slave Receiver 11.9.8.4 To operate I2C in slave receiver, follow the recommended steps below. If the main operating clock (SCLK) of the system is slower than that of SCL, load value 0x00 into I2CSDHR to make SDA change within one system clock period from the falling edge of SCL. Note that the hold time of SDA is calculated by SDAH x period of SCLK where SDAH is multiple of number of SCLK coming from I2CSDHR.
  • Page 151: Register Map

    MC96F8204 ABOV Semiconductor Co., Ltd. 11.9.9 Register Map Name Address Direction Default Description I2CCR I2C Control Register I2CSR I2C Status Register I2CSAR0 I2C Slave Address 0 Register I2CSAR1 I2C Slave Address 1 Register I2CDR I2C Data Register I2CSDHR I2C SDA Hold Time Register...
  • Page 152: Register Description For I2C

    MC96F8204 ABOV Semiconductor Co., Ltd. 11.9.11 Register Description for I2C I2CDR (I2C Data Register) : ECH I2CDR7 I2CDR6 I2CDR5 I2CDR4 I2CDR3 I2CDR2 I2CDR1 I2CDR0 Initial value : 00H I2CDR[7:0] The I2CDR transmit buffer and receive buffer share the same I/O address with this DATA register.
  • Page 153 MC96F8204 ABOV Semiconductor Co., Ltd. I2CSAR0 (I2C Slave Address 0 Register) : EBH I2CSLA06 I2CSLA05 I2CSLA04 I2CSLA03 I2CSLA02 I2CSLA01 I2CSLA00 GCALL0EN Initial value : 00H I2CSLA0[6:0] These bits configure the slave address 0 in slave mode. GCALL0EN This bit decides whether I2C allows general call address or not in I2C slave mode.
  • Page 154 MC96F8204 ABOV Semiconductor Co., Ltd. I2CCR (I2C Control Register) : E9H IICRST IICEN TXDLYENB IICIE ACKEN IMASTER STOPC STARTC Initial value : 00H IICRST Initialize Internal Registers of I2C. No effect Initialize I2C, auto cleared IICEN Activate I2C Function Block by Supplying.
  • Page 155 MC96F8204 ABOV Semiconductor Co., Ltd. I2CSR (I2C Status Register) : EAH GCALL TEND STOPD SSEL MLOST BUSY TMODE RXACK Initial value : 00H (NOTE) GCALL This bit has different meaning depending on whether I2C is master or slave. When I2C is a master, this bit represents whether it received ACK (address ACK) from slave.
  • Page 156: Flash Crc/Checksum Generator

    MC96F8204 ABOV Semiconductor Co., Ltd. 11.10 FLASH CRC/Checksum Generator 11.10.1 Overview The Flash CRC(cyclic redundancy check) generator is used to get a 16-bit CRC code from Flash ROM and a generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the functional safety standards, they offer a means of verifying the Flash memory integrity.
  • Page 157 MC96F8204 ABOV Semiconductor Co., Ltd. The CRC operation procedure in Auto CRC/Checksum mode Global interrupt Disable (EA = 0) Select Auto CRC/Checksum Mode and CRC Select CRC Clock Set CRC start address register (FCSARH/FCSARM/FCSARL) Set CRC end address register (FCEARH/FCEARM/FCEARL)
  • Page 158 MC96F8204 ABOV Semiconductor Co., Ltd. The CRC operation procedure in User CRC/Checksum mode Select User CRC/Checksum Mode and CRC Clear Flash CRC data register(FCDRH/FCDRL) Read data from the Flash ROM Write the data to FCDIN Register Read the CRC result Program Tip –...
  • Page 159 MC96F8204 ABOV Semiconductor Co., Ltd. The Checksum operation procedure in Auto CRC/Checksum mode Global interrupt Disable (EA = 0) Select Auto CRC/Checksum Mode and Checksum Select CRC Clock Set CRC start address register (FCSARH/FCSARM/FCSARL) Set CRC end address register (FCEARH/FCEARM/FCEARL)
  • Page 160 MC96F8204 ABOV Semiconductor Co., Ltd. The Checksum operation procedure in User CRC/Checksum mode Select User CRC/Checksum Mode and Checksum Clear Flash CRC data register(FCDRH/FCDRL) Read data from the Flash ROM Write the data to FCDIN Register Read the Checksum result Program Tip –...
  • Page 161: Block Diagram

    MC96F8204 ABOV Semiconductor Co., Ltd. 11.10.1 Block Diagram Flash CRC Start Address Register FCSARH/M/L (Only Auto CRC Mode) CDCL(Only User CRC Mode) FCSADR[23:0] Clear HFIRC Flash CRC Data Register HFIRC/2 FCDR[15:0] Result HFIRC/4 FCDRH/L Flash CRC Generator HFIRC/8 FCDIN (Only User CRC Mode)
  • Page 162: Flash Crc Generator Register Description

    MC96F8204 ABOV Semiconductor Co., Ltd. 11.10.3 Flash CRC Generator Register Description The flash CRC generator register consists of flash CRC start address high/middle/low register (FCSARH/ FCSARM/FCSARL), flash CRC end address high/middle/low register (FCEARH/FCEARM/FCEARL), flash CRC control register (FCCR), flash CRC data high/low register (FCDRH/FCDRL) and flash CRC data In register (FCDIN).
  • Page 163 MC96F8204 ABOV Semiconductor Co., Ltd. FCEARH (Flash CRC End Address High Register): 5051H – – – – – – – FCEARH0 – – – – – – – Initial value: 00H FCEARH0 Flash CRC End Address High NOTE) Used only to Auto CRC Mode.
  • Page 164 MC96F8204 ABOV Semiconductor Co., Ltd. FCDIN (Flash CRC Data IN Register): D7H FCDIN7 FCDIN6 FCDIN5 FCDIN4 FCDIN3 FCDIN2 FCDIN1 FCDIN0 Initial value: 00H FCDIN[7:0] Flash CRC Data In NOTE) Used only to Auto CRC Mode. FCCR (Flash CRC Control Register): 5056H –...
  • Page 165: Power Down Operation

    MC96F8204 ABOV Semiconductor Co., Ltd. Power Down Operation 12.1 Overview The MC96F8204 has two power-down modes to minimize the power consumption of the device. In power down mode, power consumption is reduced considerably. The device provides three kinds of power saving functions, Main-IDLE, Sub-IDLE and STOP mode.
  • Page 166: Idle Mode

    MC96F8204 ABOV Semiconductor Co., Ltd. 12.3 IDLE Mode The power control register is set to ‘01h’ to enter the IDLE Mode. In this mode, the internal oscillation circuits remain active. Oscillation continues and peripherals are operated normally but CPU stops. It is released by reset or interrupt.
  • Page 167: Stop Mode

    MC96F8204 ABOV Semiconductor Co., Ltd. 12.4 STOP Mode The power control register is set to ‘03H’ to enter the STOP Mode. In the stop mode, the selected oscillator, system clock and peripheral clock is stopped, but watch timer can be continued to operate with sub clock. With the clock frozen, all functions are stopped, but the on-chip RAM and control registers are held.
  • Page 168: Release Operation Of Stop Mode

    MC96F8204 ABOV Semiconductor Co., Ltd. 12.5 Release Operation of STOP Mode After STOP mode is released, the operation begins according to content of related interrupt register just before STOP mode start (Figure 12.3). If the global interrupt Enable Flag (IE.EA) is set to `1`, the STOP mode is released by the interrupt which each interrupt enable flag = `1` and the CPU jumps to the relevant interrupt service routine.
  • Page 169: Register Map

    MC96F8204 ABOV Semiconductor Co., Ltd. 12.6 Register Map Name Address Direction Default Description PCON Power Control Register Power Down Operation Register Map Table 12.2 12.7 Power Down Operation Register Description The power down operation register consists of the power control register (PCON).
  • Page 170: Reset

    MC96F8204 ABOV Semiconductor Co., Ltd. RESET 13.1 Overview The following is the hardware setting value. On Chip Hardware Initial Value Program Counter (PC) 0000h Accumulator Stack Pointer (SP) Peripheral Clock Control Register Refer to the Peripheral Registers Reset State Table 13.1 13.2...
  • Page 171: Reset Noise Canceller

    MC96F8204 ABOV Semiconductor Co., Ltd. 13.4 RESET Noise Canceller The Figure 13.2 is the noise canceller diagram for noise cancellation of RESET. It has the noise cancellation value of about 2us(@V =5V) to the low input of system reset. t < T t <...
  • Page 172 MC96F8204 ABOV Semiconductor Co., Ltd. Counting for config read start after POR is released Internal nPOR PAD RESETB “H” LVR_RESETB .. 27 28 BIT (for Config) 00 01 02 03 BIT (for Reset) 1us X 256 X 28h = about 10ms...
  • Page 173 MC96F8204 ABOV Semiconductor Co., Ltd. Process Description Remarks ① - No Operation ② - 1st POR level Detection - about 1.4V - (INT-OSC 8MHz/8)x256x28h Delay section (=10ms) - Slew Rate >= 0.05V/ms ③ - VDD input voltage must rise over than flash operating voltage for Config read - about 1.5V ~ 1.6V...
  • Page 174: External Resetb Input

    MC96F8204 ABOV Semiconductor Co., Ltd. 13.6 External RESETB Input The External RESETB is the input to a Schmitt trigger. If RESETB pin is held with low for at least 10us over within the operating voltage range and stable oscillation, it is applied and the internal state is initialized. After reset state becomes ‘1’, it needs the stabilization time with 16ms and after the stable state, the internal RESET becomes ‘1’.
  • Page 175: Brown Out Detector Processor

    MC96F8204 ABOV Semiconductor Co., Ltd. 13.7 Brown Out Detector Processor The MC96F8204 has an On-chip brown-out detection circuit (BOD) for monitoring the VDD level during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be selected by LVRVS[3:0] bit to be 1.60V, 2.05V, 2.15V, 2.25V,2.37V, 2.50V, 2.65V, 2.82V, 3.01V, 3.22V, 3.47V, 3.76V, 4.10V, 4.51V.
  • Page 176 MC96F8204 ABOV Semiconductor Co., Ltd. “H” “H” Internal nPOR “H” PAD RESETB LVR_RESETB BIT (for Config) ..27 28 00 01 02 BIT (for Reset) 1us X 256 X 28h = about 10ms Config Read 1us X 4096 X 4h = about 16ms...
  • Page 177: Lvi Block Diagram

    MC96F8204 ABOV Semiconductor Co., Ltd. 13.8 LVI Block Diagram 2.05V 2.15V 2.25V 2.37V 2.50V 2.65V Reference 2.82V LVI Circuit LVIF Voltage 3.01V Generator 3.22V 3.47V 3.76V 4.10V LVIEN 4.51V LVILS[3:0] Figure 13.12 LVI Diagram 13.9 Register Map Name Address Direction...
  • Page 178: Register Description For Reset Operation

    MC96F8204 ABOV Semiconductor Co., Ltd. 13.11 Register Description for Reset Operation RSTFR (Reset Flag Register) : E8H – – – PORF EXTRF WDTRF OCDRF LVRF – – – Initial value : 80H Power-On Reset flag bit. The bit is reset by writing ‘0’ to this bit.
  • Page 179 MC96F8204 ABOV Semiconductor Co., Ltd. LVRCR (Low Voltage Reset Control Register) : D8H – – LVRST LVRVS3 LVRVS2 LVRVS1 LVRVS0 LVREN – – Initial value : 00H LVRST LVR Enable when Stop Release Not effect at stop release LVR enable at stop release NOTE) When this bit is ‘1’, the LVREN bit is cleared to ‘0’...
  • Page 180 MC96F8204 ABOV Semiconductor Co., Ltd. LVICR (Low Voltage Indicator Control Register) : 86H – – LVIF LVIEN LVILS3 LVILS2 LVILS1 LVILS0 – – Initial value : 00H LVIF Low Voltage Indicator Flag Bit No detection Detection LVIEN LVI Enable/Disable Disable...
  • Page 181: On-Chip Debug System

    MC96F8204 ABOV Semiconductor Co., Ltd. On-chip Debug System 14.1 Overview 14.1.1 Description On-chip debug system (OCD) of MC96F8204 can be used for programming the non-volatile memories and on-chip debugging. Detail descriptions for programming via the OCD interface can be found in the following chapter.
  • Page 182: Feature

    MC96F8204 ABOV Semiconductor Co., Ltd. 14.1.2 Feature − Two-wire external interface: 1-wire serial clock input, 1-wire bi-directional serial data bus − Debugger Access to: • All Internal Peripheral Units • Internal data RAM • Program Counter • Flash and Data EEPROM Memories −...
  • Page 183: Two-Pin External Interface

    MC96F8204 ABOV Semiconductor Co., Ltd. 14.2 Two-Pin External Interface 14.2.1 Basic Transmission Packet • 10-bit packet transmission using two-pin interface. • 1-packet consists of 8-bit data, 1-bit parity and 1-bit acknowledge. • Parity is even of ‘1’ for 8-bit data in transmitter.
  • Page 184: Packet Transmission Timing

    MC96F8204 ABOV Semiconductor Co., Ltd. 14.2.2 Packet Transmission Timing Data Transfer 14.2.2.1 DSDA acknowledgement acknowledgement signal from receiver signal from receiver DSCL START STOP Figure 14.3 Data Transfer on the Twin Bus Bit Transfer 14.2.2.2 DSDA DSCL data line change...
  • Page 185: Start And Stop Condition

    MC96F8204 ABOV Semiconductor Co., Ltd. Start and Stop Condition 14.2.2.3 DSDA DSDA DSCL DSCL START condition STOP condition Figure 14.5 Start and Stop Condition Acknowledge Bit 14.2.2.4 Data output By transmitter no acknowledge Data output By receiver acknowledge DSCL from...
  • Page 186: Connection Of Transmission

    MC96F8204 ABOV Semiconductor Co., Ltd. 14.2.3 Connection of Transmission Two-pin interface connection uses open-drain(wire-AND bidirectional I/O). pull - up resistors DSDA(Debugger Serial Data Line) DSCL(Debugger Serial Clock Line) DSCL DSDA DSCL DSDA DSDA DSDA DSCL DSCL Target Device(Slave) Host Machine(Master) Current source for DSCL to fast 0 to 1 transition in high speed mode Figure 14.8...
  • Page 187: Flash Memory

    MC96F8204 ABOV Semiconductor Co., Ltd. Flash Memory 15.1 Overview 15.1.1 Description MC96F8204 incorporates flash memory to which a program can be written, erased, and overwritten while mounted on the board. The flash memory can be read by ‘MOVC’ instruction and it can be programmed in OCD, serial ISP mode or user program mode.
  • Page 188: Flash Program Rom Structure

    MC96F8204 ABOV Semiconductor Co., Ltd. 15.1.2 Flash Program ROM Structure 00FFFH Sector 127 00FE0H 00FE0H 00FDFH Sector 126 00FC0H 00FC0H 00FBFH Sector 125 00FA0H 00FA0H 00F9FH Sector 124 Flash Sector Address Address Sector 2 00040H 00040H 0003FH Sector 1 00020H...
  • Page 189: Register Map

    MC96F8204 ABOV Semiconductor Co., Ltd. 15.1.3 Register Map Name Address Direction Default Description FSADRH Flash Sector Address High Register FSADRM Flash Sector Address Middle Register FSADRL Flash Sector Address Low Register FIDR Flash Identification Register FMCR Flash Mode Control Register Flash Memory Register Map Table 15.1...
  • Page 190: Register Description For Flash

    MC96F8204 ABOV Semiconductor Co., Ltd. 15.1.5 Register Description for Flash FSADRH (Flash Sector Address High Register) : FAH – – – – FSADRH3 FSADRH 2 FSADRH1 FSADRH0 – – – – Initial value : 00H FSADRH[3:0] Flash Sector Address High...
  • Page 191 MC96F8204 ABOV Semiconductor Co., Ltd. FMCR (Flash Mode Control Register) : FEH – – – – FMBUSY FMCR2 FMCR1 FMCR0 – – – – Initial value : 00H FMBUSY Flash Mode Busy Bit. This bit will be used for only debugger.
  • Page 192: Serial In-System Program (Isp) Mode

    MC96F8204 ABOV Semiconductor Co., Ltd. 15.1.6 Serial In-System Program (ISP) Mode Serial in-system program uses the interface of debugger which uses two wires. Refer to chapter 14 in details about debugger 15.1.7 Protection Area (User program mode) MC96F8204 can program its own flash memory (protection area). The protection area can not be erased or programmed.
  • Page 193: Erase Mode

    MC96F8204 ABOV Semiconductor Co., Ltd. 15.1.8 Erase Mode The sector erase program procedure in user program mode Page buffer clear (FMCR=0x01) Write ‘0’ to page buffer Set flash sector address register (FSADRH/FSADRM/FSADRL). Set flash identification register (FIDR). (Note) Check the UserID for to prevent the invalid work Set flash mode control register (FMCR).
  • Page 194: Write Mode

    MC96F8204 ABOV Semiconductor Co., Ltd. 15.1.9 Write Mode The sector Write program procedure in user program mode Page buffer clear (FMCR=0x01) Write data to page buffer Set flash sector address register (FSADRH/FSADRM/FSADRL). Set flash identification register (FIDR). (Note1) Check the UserID for to prevent the invalid work Set flash mode control register (FMCR).
  • Page 195 MC96F8204 ABOV Semiconductor Co., Ltd. The Byte Write program procedure in user program mode Page buffer clear (FMCR=0x01) Write data to page buffer Set flash sector address register (FSADRH/FSADRM/FSADRL). Set flash identification register (FIDR). (Note1) Check the UserID for to prevent the invalid work Set flash mode control register (FMCR).
  • Page 196: Protection For Invalid Erase/Write

    MC96F8204 ABOV Semiconductor Co., Ltd. 15.1.10 Protection for Invalid Erase/Write It should be taken care to the flash erase/write programming in code. You must make preparations for invalid jump to the flash erase/write code by malfunction, noise, and power off.
  • Page 197 MC96F8204 ABOV Semiconductor Co., Ltd. The flash sector address (FSADRH/FSADRM/FSADRL) should always keep the address of the flash which is used for data area. For example, The FSADRH/FSADRM is always 0x00/0x0f” if 0x0f00 to 0x0fff is used for data. Overview of main...
  • Page 198: Flow Of Protection For Invalid Erase/Write

    MC96F8204 ABOV Semiconductor Co., Ltd. Flow of Protection for Invalid Erase/Write 15.1.10.1 Start Work1 Decide to write/erase Set Flags on flash Work2 Check the flag for Match Write UserID1/2/3 UserID Work3 Check the UserID for Match Write/Erase Flash write/erase flash...
  • Page 199: Read Mode

    MC96F8204 ABOV Semiconductor Co., Ltd. 15.1.11 Read Mode The Reading program procedure in user program mode Load receive data from flash memory on MOVC instruction by indirectly addressing mode. Program Tip – reading A,#0 DPH,#0x0F DPL,#0xA0 ;flash memory address MOVC A,@A+DPTR ;read data from flash memory...
  • Page 200: Configure Option

    MC96F8204 ABOV Semiconductor Co., Ltd. Configure Option 16.1 Configure Option Control The data for configure option should be written in the configure option area (001EH – 001FH) by programmer (Writer tools). CONFIGURE OPTION 1 : ROM Address 001FH – –...
  • Page 201: Appendix

    MC96F8204 ABOV Semiconductor Co., Ltd. APPENDIX 17.1 Instruction Table Instructions are either 1, 2 or 3bytes long as listed in the ‘Bytes’ column below. Each instruction takes either 1, 2 or 4 machine cycles to execute as listed in the following table. 1 machine cycle comprises 2 system clock cycles.
  • Page 202 MC96F8204 ABOV Semiconductor Co., Ltd. LOGICAL Mnemonic Description Bytes Cycles Hex code ANL A,Rn AND register to A 58-5F ANL A,dir AND direct byte to A ANL A,@Ri AND indirect memory to A 56-57 ANL A,#data AND immediate to A...
  • Page 203 MC96F8204 ABOV Semiconductor Co., Ltd. DATA TRANSFER Mnemonic Description Bytes Cycles Hex code MOV A,Rn Move register to A E8-EF MOV A,dir Move direct byte to A MOV A,@Ri Move indirect memory to A E6-E7 MOV A,#data Move immediate to A...
  • Page 204 MC96F8204 ABOV Semiconductor Co., Ltd. BRANCHING Mnemonic Description Bytes Cycles Hex code ACALL addr 11 Absolute jump to subroutine 11→F1 LCALL addr 16 Long jump to subroutine Return from subroutine RETI Return from interrupt AJMP addr 11 Absolute jump unconditional 01→E1...
  • Page 205: Flash Protection For Invalid Erase/Write

    MC96F8204 ABOV Semiconductor Co., Ltd. 17.2 Flash Protection for Invalid Erase/Write  Overview This is example to prevent changing code or data in flash by abnormal operation(noise, unstable power, malfunction, etc…).  How to protect the flash • Divide into decision and execution to Erase/Write in flash.
  • Page 206 MC96F8204 ABOV Semiconductor Co., Ltd.  Flowchart Start Initial ① Set LVR/LVI more than 2.0V Start Main Loop Working ③ Write Flash? Set User_ID1 ② Working ③ Check User_ID1? Set User_ID2 Working Check User_ID2? Set User_ID3 ③ Working Write Flash Set FSADDRH/M/L ④...
  • Page 207 Initialize User_ID1/2/3 Set Flash Sector Address to Dummy Address • Sample Source Refer to the ABOV homepage. It is created based on the MC97F2664. Each product should be modified according to the Page Buffer Size and Flash Size  Etc •...
  • Page 208: Table Of Contents

    MC96F8204 ABOV Semiconductor Co., Ltd. Table of contents Revision history ................................2 Overview ................................... 3 1.1. Description ................................3 Features ................................4 Development tools .............................. 5 1.3.1 Compiler ..............................5 1.3.2 OCD(On-chip debugger) emulator and debugger ..................5 1.3.3 Programmer ..............................6 MTP programming ..............................
  • Page 209 MC96F8204 ABOV Semiconductor Co., Ltd. 8.4.4 Extended SFR Map ........................... 54 8.4.5 SFR Map ..............................55 I/O Ports .................................. 57 I/O Ports ................................57 Port Register ..............................57 9.2.1 Data Register (Px) ............................. 57 9.2.2 Direction Register (PxIO) .......................... 57 9.2.3...
  • Page 210 MC96F8204 ABOV Semiconductor Co., Ltd. 11.3.4 Register Map ............................. 91 11.3.5 Watch Dog Timer Register Description ..................... 91 11.3.6 Register Description for Watch Dog Timer ....................92 11.4 Watch Timer ..............................93 11.4.1 Overview ..............................93 11.4.2 Block Diagram ............................93 11.4.3...
  • Page 211 MC96F8204 ABOV Semiconductor Co., Ltd. 11.9.3 I2C Bit Transfer ............................141 11.9.4 Start / Repeated Start / Stop ........................141 11.9.5 Data Transfer ............................142 11.9.6 I2C Acknowledge ............................. 143 11.9.7 Synchronization / Arbitration ........................144 11.9.8 Operation ..............................145 11.9.8.1...
  • Page 212 MC96F8204 ABOV Semiconductor Co., Ltd. 15.1.5 Register Description for Flash ......................... 190 15.1.6 Serial In-System Program (ISP) Mode ....................192 15.1.7 Protection Area (User program mode) ....................192 15.1.8 Erase Mode ............................. 193 15.1.9 Write Mode .............................. 194 15.1.10 Protection for Invalid Erase/Write ......................196 15.1.10.1...

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