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CMOS single-chip 8-bit MCU with 12-bit A/D converter MC96F8204 Main features User’s manual 8-bit Microcontroller With High Speed 8051 CPU Basic MCU Function V 1.4 – 4Kbytes Flash Code Memory – 256bytes IRAM Built-in Analog Function – Power-On Reset and Low Voltage Detect Reset –...
The information, diagrams and other data in this manual are correct and reliable; however, ABOV Semiconductor is in no way responsible for any violations of patents or other rights of the third party generated by the use of this manual.
MC96F8204 ABOV Semiconductor Co., Ltd. Overview 1.1. Description The MC96F8204 is advanced CMOS 8-bit microcontroller with 4 Kbytes of FLASH. This is powerful microcontroller which provides a highly flexible and cost effective solution to many embedded control applications. This provides the...
1.3.2 OCD(On-chip debugger) emulator and debugger The OCD (On Chip Debug) emulator supports ABOV Semiconductor’s 8051 series MCU emulation. The OCD interface uses two-wire interfacing between PC and MCU which is attached to user’s system. The OCD can read or change the value of MCU internal memory and I/O peripherals. And the OCD also controls MCU internal debugging logic, it means OCD controls emulation, step run, monitoring, etc.
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MC96F8204 ABOV Semiconductor Co., Ltd. OCD emulator: It can write code to MCU device too, because OCD debugger supports ISP (In System Programming).It does not require additional H/W, except developer’s target system. Gang programmer: E-GANG4 and E-GANG6 It can run PC controlled mode.
MC96F8204 ABOV Semiconductor Co., Ltd. MTP programming 1.4.1 Overview The program memory of MC96F8204 is MTP Type. This flash is accessed by serial data format. There are four pins(DSCL, DSDA, VDD, VSS) for programming/reading the flash. During programming Main chip...
MC96F8204 ABOV Semiconductor Co., Ltd. 1.4.3 Circuit Design Guide At the FLASH programming, the programming tool needs 4 signal lines that are DSCL, DSDA, VDD, and VSS. When you design the PCB circuits, you should consider the usage of these signal lines for the on-board programming.
MC96F8204 ABOV Semiconductor Co., Ltd. Block diagram Flash CORE IRAM M8051 256B On-chip debug In-system programming General purpose I/O Power control 18 ports normal I/O Power on reset Low voltage reset Low voltage indicator Power down mode Watchdog timer 1 channel, 8-bit...
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MC96F8204 ABOV Semiconductor Co., Ltd. P05/AN5/AVREF/EC1/RESETB P02/AN2/EINT11/T1O/PWM1O P04/AN4/EINT10/EC2/SDA P03/AN3/EINT12/T2O/PWM2O/SCL P06/AN6/SS/XIN/SXIN P01/AN1/EINT1/RXD/MISO/DSCL P07/AN7/SCK/XOUT/SXOUT P00/AN0/EINT0/TXD/MOSI/DSDA NOTE) On On-Chip Debugging, ISP uses P0[1:0] pin as DSCL, DSDA. The P10-P17 and P20-P21 pins should be selected as a push-pull output or an input with pull-up resistor by software control when the 10-pin package is used.
MC96F8204 ABOV Semiconductor Co., Ltd. Pin Description Function @RESET Shared with Name AN0/EINT0/TXD/MOSI/DSDA AN1/EINT1/RXD/MISO/DSCL AN2/EINT11/T1O/PWM1O Port 0 is a bit-programmable I/O port which can be configured as a schmitt-trigger input, a push-pull AN3/EINT12/T2O/PWM2O/SCL output, or an open-drain output. Input AN4/EINT10/EC2/SDA A pull-up resistor can be specified in 1-bit unit.
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MC96F8204 ABOV Semiconductor Co., Ltd. Function @RESET Shared with Name AVREF A/D converter reference voltage Input P05/AN5/EC1/RESETB P00/EINT0/TXD/MOSI/DSDA P01/EINT1/RXD/MISO/DSCL P02/EINT11/T1O/PWM1O P03/EINT12/T2O/PWM2O/SCL A/D converter analog input channels Input P04/EINT10/EC2/SDA P05/AVREF/EC1/RESETB P06/SS/XIN/SXIN P07/SCK/XOUT/SXOUT System reset pin with a pull-up resistor when it is...
MC96F8204 ABOV Semiconductor Co., Ltd. Port Structures General Purpose I/O Port Level Shift (VDC to ExtVDD) Level Shift (ExtVDD to VDC) PULL-UP REGISTER OPEN DRAIN REGISTER DATA REGISTER SUB-FUNC DATA OUTPUT SUB-FUNC ENABLE SUB-FUNC DIRECTION DIRECTION REGISTER CMOS or Schmitt Level...
MC96F8204 ABOV Semiconductor Co., Ltd. External Interrupt I/O Port Level Shift (VDC to ExtVDD) Level Shift (ExtVDD to VDC) PULL-UP REGISTER OPEN DRAIN REGISTER DATA REGISTER SUB-FUNC DATA OUTPUT SUB-FUNC ENABLE SUB-FUNC DIRECTION DIRECTION REGISTER EXTERNAL INTERRUPT POLARITY REG. INTERRUPT...
MC96F8204 ABOV Semiconductor Co., Ltd. Electrical Characteristics Absolute Maximum Ratings Parameter Symbol Rating Unit Note – Supply Voltage -0.3 ~ +6.5 -0.3 ~ VDD+0.3 Voltage on any pin with respect to VSS -0.3 ~ VDD+0.3 Maximum current output sourced by (I...
MC96F8204 ABOV Semiconductor Co., Ltd. 7.12 UART Characteristics =-40°C ~ +85°C, VDD=1.8V ~ 5.5V, f =11.1MHz) Parameter Symbol Unit Serial port clock cycle time 1250 x 16 1650 – Output data setup to clock rising edge x 13 – –...
MC96F8204 ABOV Semiconductor Co., Ltd. 7.14 Data Retention Voltage in Stop Mode =-40°C ~ +85°C, VDD=1.8V ~ 5.5V) Parameter Symbol Conditions Unit – – Data retention supply voltage DDDR VDDR= 1.8V, (T = 25°C), – – Data retention supply current...
MC96F8204 ABOV Semiconductor Co., Ltd. 7.21 Operating Voltage Range =0.4 to 12MHz)(Ceramic) =0.4 to 12MHz)(Crystal) 12.0MHz 12.0MHz 4.2MHz 4.2MHz 0.4MHz 0.4MHz Supply voltage (V) Supply voltage (V) Figure 7.14 Operating Voltage Range (Main OSC) =32 to 38kHz) 32.768kHz Supply voltage (V) Figure 7.15...
MC96F8204 ABOV Semiconductor Co., Ltd. 7.22 Recommended Circuit and Layout This 0.1uF capacitor should be within 1cm from the VDD pin of MCU on the VDD VCC PCB layout. DC Power 0.1uF 0.1uF The MCU power line (VDD and VSS)
MC96F8204 ABOV Semiconductor Co., Ltd. 7.23 Recommended Circuit and Layout with SMPS Power SMPS Side MCU Side SMPS 1. The C1 capacitor is to flatten out the voltage of the SMPS power, VCC. √ Recommended C1: 470uF/25V more. 2. The R1 and C2 are the RC filter for VDD and suppress the ripple of VCC.
MC96F8204 ABOV Semiconductor Co., Ltd. 7.24 Typical Characteristics These graphs and tables provided in this section are only for design guidance and are not tested or guaranteed. In graphs or tables some data are out of specified operating range (e.g. out of specified VDD range). This is only for information and devices are guaranteed to operate properly only within the specified range.
MC96F8204 ABOV Semiconductor Co., Ltd. Memory The MC96F8204 addresses two separate address memory stores: Program memory and Data memory. The logical separation of Program and Data memory allows Data memory to be accessed by 8-bit addresses, which makes the 8- bit CPU access the data memory more rapidly.
MC96F8204 ABOV Semiconductor Co., Ltd. Data Memory Upper 128bytes Special Function Registers Internal RAM 128bytes (Indirect Addressing) (Direct Addressing) Lower 128bytes Internal RAM (Direct or Indirect Addressing) Figure 8.2 Data Memory Map The internal data memory space is divided into three blocks, which are generally referred to as the lower 128 bytes, upper 128 bytes, and SFR space.
MC96F8204 ABOV Semiconductor Co., Ltd. Extended SFR Area This area has no relation with RAM/FLASH. It can be read and written to through SFR with 8-bit unit. 505FH Extended Special Function Register (Indirect Addressing) 5050H Not used 0000H Figure 8.4...
MC96F8204 ABOV Semiconductor Co., Ltd. 8.4.3 SFR Map @Reset Address Function Symbol P0 Data Register Stack Pointer Data Pointer Register Low Data Pointer Register High Data Pointer Register Low 1 DPL1 Data Pointer Register High 1 DPH1 – – Low Voltage Indicator Control Register LVICR –...
MC96F8204 ABOV Semiconductor Co., Ltd. I/O Ports I/O Ports The MC96F8204 has three groups of I/O ports (P0~P2). Each can be easily configured by software as I/O pin, internal pull up and open-drain pin to meet various system configurations and design requirements. Also P0 include function that can generate interrupt according to change of state of the pin.
MC96F8204 ABOV Semiconductor Co., Ltd. P0 Port 9.3.1 P0 Port Description P0 is 8-bit I/O port. P0 control registers consist of P0 data register (P0), P0 direction register (P0IO), debounce enable register (P0DB), P0 pull-up resistor selection register (P0PU), and P0 open-drain selection register (P0OD). Refer to the port function selection registers for the P0 function selection.
MC96F8204 ABOV Semiconductor Co., Ltd. P1 Port 9.4.1 P1 Port Description P1 is 8-bit I/O port. P1 control registers consist of P1 data register (P1), P1 direction register (P1IO), P1 pull-up resistor selection register (P1PU), and P1 open-drain selection register (P1OD). Refer to the port function selection registers for the P1 function selection.
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MC96F8204 ABOV Semiconductor Co., Ltd. P1FSR (Port 1 Function Selection Register) : A7H – – – P1FSR4 P1FSR3 P1FSR2 P1FSR1 P1FSR0 – – – Initial value : 00H P1FSR4 P14 Function select I/O Port SCK Function P1FSR3 P13 Function select...
MC96F8204 ABOV Semiconductor Co., Ltd. P2 Port 9.5.1 P2 Port Description P2 is 2-bit I/O port. P2 control registers consist of P2 data register (P2), P2 direction register (P2IO), P2 pull-up resistor selection register (P2PU), and P2 open-drain selection register (P2OD). Refer to the port function selection registers for the P2 function selection.
MC96F8204 ABOV Semiconductor Co., Ltd. Interrupt Controller 10.1 Overview The MC96F8204 supports up to 15 interrupt sources. The interrupts have separate enable register bits associated with them, allowing software control. They can also have four levels of priority assigned to them. The non-maskable interrupt source is always enabled with a higher priority than any other interrupt source, and is not controllable by software.
MC96F8204 ABOV Semiconductor Co., Ltd. 10.2 External Interrupt The external interrupt on INT0, INT1, INT10, INT11 and INT12 pins receive various interrupt request depending on the external interrupt polarity 0 register (EIPOL0) and external interrupt polarity 1 register (EIPOL1) as shown in Figure 10.1.
MC96F8204 ABOV Semiconductor Co., Ltd. 10.4 Interrupt Vector Table The interrupt controller supports 24 interrupt sources as shown in the Table 10-2. When interrupt is served, long call instruction (LCALL) is executed and program counter jumps to the vector address. All interrupt requests have their own priority order.
MC96F8204 ABOV Semiconductor Co., Ltd. 10.5 Interrupt Sequence An interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to ‘0’ by a reset or an instruction. Interrupt acceptance always generates at last cycle of the instruction. So instead of fetching the current instruction, CPU executes internally LCALL instruction and saves the PC at stack.
MC96F8204 ABOV Semiconductor Co., Ltd. 10.6 Effective Timing after Controlling Interrupt Bit Case a) Control Interrupt Enable Register (IE, IE1, IE2, IE3) Interrupt Enable Register command After executing IE set/clear, enable register is effective. Next Instruction Next Instruction Figure 10.4...
MC96F8204 ABOV Semiconductor Co., Ltd. 10.7 Multi Interrupt If two requests of different priority levels are received simultaneously, the request of higher priority level is served first. If more than one interrupt request are received, the interrupt polling sequence determines which request is served first by hardware.
MC96F8204 ABOV Semiconductor Co., Ltd. 10.12 Interrupt Register Overview 10.12.1 Interrupt Enable Register (IE, IE1, IE2, IE3) Interrupt enable register consists of global interrupt control bit (EA) and peripheral interrupt control bits. Total 24 peripherals are able to control interrupt.
MC96F8204 ABOV Semiconductor Co., Ltd. 10.12.6 Interrupt Register Description The interrupt register is used for controlling interrupt functions. Also it has external interrupt control registers. The interrupt register consists of interrupt enable register (IE), interrupt enable register 1 (IE1), interrupt enable register 2 (IE2) and interrupt enable register 3 (IE3).
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MC96F8204 ABOV Semiconductor Co., Ltd. EIFLAG (External Interrupt Flag 0 Register) : C0H – T0IFR IICIFR FLAG12 FLAG11 FLAG10 FLAG1 FLAG0 – Initial value : 00H When T0 interrupt occurs, this bit becomes ‘1’. For clearing bit, write ‘0’ to this bit or T0IFR auto clear by INT_ACK signal.
MC96F8204 ABOV Semiconductor Co., Ltd. Peripheral Hardware 11.1 Clock Generator 11.1.1 Overview As shown in Figure 11.1, the clock generator produces the basic clock pulses which provide the system clock to be supplied to the CPU and the peripheral hardware. It contains main/sub-frequency clock oscillator. The main/sub clock operation can be easily obtained by attaching a crystal between the XIN/SXIN and XOUT/SXOUT pin, respectively.
MC96F8204 ABOV Semiconductor Co., Ltd. 11.1.3 Register Map Name Address Direction Default Description SCCR System and Clock Control Register OSCCR Oscillator Control Register LIFSR LFIRC Frequency Selection Register XTFLSR X-tal Filter Selection Register Clock Generator Register Map Table 11.1 11.1.4 Clock Generator Register Description The clock generator register uses clock control for system operation.
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MC96F8204 ABOV Semiconductor Co., Ltd. OSCCR (Oscillator Control Register) : C8H – LFIRCE HFIRCS2 HFIRCS1 HFIRCS0 HFIRCE XCLKE SCLKE – Initial value : 08H LFIRCE Control the operation of the low frequency internal RC oscillator Disable operation of LF INT-RC OSC...
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MC96F8204 ABOV Semiconductor Co., Ltd. XTFLSR (X-tal Filter Selection Register): BFH WTP4 WTP3 WTP2 WTP1 WTP0 XRNS2 XRNS1 XRNS0 Initial value: 00H Write Identification bits. These bits are automatically cleared to “00000b” immediately WTP[4:0] after XTFLSR write. 0x00 on read.
MC96F8204 ABOV Semiconductor Co., Ltd. 11.2 Basic Interval Timer 11.2.1 Overview The MC96F8204 has one 8-bit basic interval timer that is free-run and can’t stop. Block diagram is shown in Figure 11.2. In addition, the basic interval timer generates the time base for watchdog timer counting. It also provides a basic interval timer interrupt (BITIFR).
MC96F8204 ABOV Semiconductor Co., Ltd. 11.2.4 Basic Interval Timer Register Description The basic interval timer register consists of basic interval timer counter register (BITCNT) and basic interval timer control register (BITCR). If BCLR bit is set to ‘1’, BITCNT becomes ‘0’ and then counts up. After 1 machine cycle, BCLR bit is cleared to ‘0’...
MC96F8204 ABOV Semiconductor Co., Ltd. 11.3 Watch Dog Timer 11.3.1 Overview The watchdog timer rapidly detects the CPU malfunction such as endless looping caused by noise or something like that, and resumes the CPU to the normal state. The watchdog timer signal for malfunction detection can be used as either a CPU reset or an interrupt request.
MC96F8204 ABOV Semiconductor Co., Ltd. 11.4 Watch Timer 11.4.1 Overview The watch timer has the function for RTC (Real Time Clock) operation. It is generally used for RTC design. The internal structure of the watch timer consists of the clock source select circuit, timer counter circuit, output select circuit and watch timer control register.
MC96F8204 ABOV Semiconductor Co., Ltd. 11.4.3 Register Map Name Address Direction Default Description WTCNT Watch Timer Counter Register WTDR Watch Timer Data Register WTCR Watch Timer Control Register Watch Timer Register Map Table 11.4 11.4.4 Watch Timer Register Description The watch timer register consists of watch timer counter register (WTCNT), watch timer data register (WTDR) and watch timer control register (WTCR).
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MC96F8204 ABOV Semiconductor Co., Ltd. WTCR (Watch Timer Control Register): 9EH – – WTEN WTIFR WTIN1 WTIN0 WTCK1 WTCK0 – – Initial value: 00H WTEN Control Watch Timer Disable Enable When WT Interrupt occurs, this bit becomes ‘1’. For clearing bit, write ‘0’ to this bit or WTIFR automatically clear by INT_ACK signal.
MC96F8204 ABOV Semiconductor Co., Ltd. 11.5 Timer 0 11.5.1 Overview The 8-bit timer 0 consists of multiplexer, timer 0 counter register, timer 0 data register, timer 0 capture data register and timer 0 control register (T0CNT, T0DR, T0CDR, T0CR). It has two operating modes: −...
MC96F8204 ABOV Semiconductor Co., Ltd. 11.5.2 8-bit Timer/Counter Mode The 8-bit timer/counter mode is selected by control register as shown in Figure 11.5. The 8-bit timer have counter and data register. The counter register is increased by internal. Timer 0 can use the input clock with one of 2, 4, 8, 32, 128, 512 and 2048 prescaler division rates (T0CK[2:0]).
MC96F8204 ABOV Semiconductor Co., Ltd. 11.5.3 8-bit Capture Mode The timer 0 capture mode is set by T0MS as ‘1’. The clock source can use the internal/external clock. Basically, it has the same function as the 8-bit timer/counter mode and the interrupt occurs when T0CNT is equal to T0DR. T0CNT value is automatically cleared by match signal and it can be also cleared by software (T0CC).
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MC96F8204 ABOV Semiconductor Co., Ltd. T0CDR Load T0CNT Value Count Pulse Period Up-count TIME Ext. EINT10 PIN Interrupt Request (FLAG10) Interrupt Interval Period Figure 11.9 Input Capture Mode Operation for Timer 0 T0CNT Interrupt Request (T0IFR) Ext. EINT10 PIN Interrupt...
MC96F8204 ABOV Semiconductor Co., Ltd. 11.6.3 16-bit Capture Mode The 16-bit timer 1/2 capture mode is set by TnMS[1:0] as ‘01’. The clock source can use the internal/external clock. Basically, it has the same function as the 16-bit timer/counter mode and the interrupt occurs when TnCNTH/TnCNTL is equal to TnADRH/TnADRL.
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MC96F8204 ABOV Semiconductor Co., Ltd. TnBDRH/L Load TnCNTH/L Value Count Pulse Period Up-count TIME Ext. EINT1n PIN Interrupt Request (FLAG1n) Interrupt Interval Period Figure 11.15 Input Capture Mode Operation for Timer 1/2 FFFF FFFF TnCNTH/L Interrupt Request (TnIFR) Ext. EINT1n PIN...
MC96F8204 ABOV Semiconductor Co., Ltd. 11.6.4 16-bit PPG Mode The timer 1/2 has a PPG (Programmable Pulse Generation) function. In PPG mode, TnO/PWMnO pin outputs up to 16-bit resolution PWM output. This pin should be configured as a PWM output by setting P0FSRL[5:4](T1), P0FSRL[7:6](T2) to ‘01’.
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MC96F8204 ABOV Semiconductor Co., Ltd. Repeat Mode(TnMS = 11b) and "Start High"(TnPOLA = 0b). Clear and Start Set TnEN Timer n clock Counter TnADRH/L Tn Interrupt 1. TnBDRH/L(5) < TnADRH/L PWMnO B Match A Match 2. TnBDRH/L >= TnADRH/L PWMnO A Match 3.
MC96F8204 ABOV Semiconductor Co., Ltd. 11.6.5 Block Diagram 16-bit A Data Register TnADRH/TnADRL A Match Reload TnCC TnEN RLDnEN TnECE TnCK[2:0] INT_ACK Buffer Register A To other block Clear Edge Detector A Match To interrupt TnIFR fx/1 TnEN block Comparator...
MC96F8204 ABOV Semiconductor Co., Ltd. 11.6.7 Timer/Counter 1/2 Register Description The timer/counter 1/2 register consists of timer 1/2 A data high register (TnADRH), timer 1/2 A data low register (TnADRL), timer 1/2 B data high register (TnBDRH), timer 1/2 B data low register (TnBDRL), timer 1/2 control high register (TnCRH) and timer 1/2 control low register (TnCRL).
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MC96F8204 ABOV Semiconductor Co., Ltd. TnCRH (Timer n Control High Register) : 99H/B1H, Where n = 1 and 2 – – – – TnEN TnMS1 TnMS0 TnCC – – – – Initial value : 00H TnEN Control Timer n Timer n disable...
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MC96F8204 ABOV Semiconductor Co., Ltd. TnCRL (Timer n Control Low Register) : 98H/B0H, Where n = 1 and 2 TnCK2 TnCK1 TnCK0 TnIFR RLDnEN TnPOL TnECE TnCNTR Initial value : 00H TnCK[2:0] Select Timer n clock source. fx is main system clock frequency...
MC96F8204 ABOV Semiconductor Co., Ltd. 11.7 12-bit A/D Converter 11.7.1 Overview The analog-to-digital converter (A/D) allows conversion of an analog input signal to corresponding 12-bit digital value. The A/D module has eight analog inputs. The output of the multiplexer is the input into the converter which generates the result through successive approximation.
MC96F8204 ABOV Semiconductor Co., Ltd. 11.7.3 Block Diagram TRIG ADSEL[3:0] ADST Start (Select one input pin T1 A match signal of the assigned pins) Clock ADCLK Selector Clear AFLAG Input Pins Comparator Control To interrupt ADCIFR Logic block VDD19 Clear...
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MC96F8204 ABOV Semiconductor Co., Ltd. SET ADCCRH Select ADC Clock and Data Align Bit. SET ADCCRL ADC enable & Select AN Input Channel. Converting START Start ADC Conversion. If Conversion is completed, AFLAG is set “1” and ADC interrupt is AFLAG = 1? occurred.
MC96F8204 ABOV Semiconductor Co., Ltd. 11.7.7 Register Description for ADC ADCDRH (A/D Converter Data High Register) : CFH ADDM11 ADDM10 ADDM9 ADDM8 ADDM7 ADDM6 ADDM5 ADDM4 ADDL11 ADDL10 ADDL9 ADDL8 Initial value : xxH ADDM[11:4] MSB align, A/D Converter High Data (8-bit)
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MC96F8204 ABOV Semiconductor Co., Ltd. ADCCRH (A/D Converter Control High Register) : A1H – – – ADCIFR TRIG ALIGN CKSEL1 CKSEL0 – – – Initial value : 00H When ADC Interrupt occurs, this bit becomes ‘1’. For clearing bit, write ‘0’ to this bit or ADCIFR auto clear by INT_ACK signal.
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MC96F8204 ABOV Semiconductor Co., Ltd. ADCCRL (A/D Converter Control Low Register) : A0H STBY ADST REFSEL AFLAG ADSEL3 ADSEL2 ADSEL1 ADSEL0 Initial value : 00H STBY Control Operation of A/D (The ADC module is automatically disabled at stop mode) ADC module disable...
MC96F8204 ABOV Semiconductor Co., Ltd. 11.8 USART 11.8.1 Overview The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device. The main features are listed below. − Full Duplex Operation (Independent Serial Receive and Transmit Registers) −...
MC96F8204 ABOV Semiconductor Co., Ltd. 11.8.3 USART Clock Generation USTBD DBLSn SCLK (USTBD+1) Prescaling Up-Counter txclk SCLK MASTERn Edge Sync Register USTMS[1:0] Detector CPOL rxclk Figure 11.26 Clock Generation Block Diagram (USART) The clock generation logic generates the base clock for the transmitter and receiver. The USART supports four modes of clock operation and those are normal asynchronous, double speed asynchronous, master synchronous and slave synchronous mode.
MC96F8204 ABOV Semiconductor Co., Ltd. 11.8.4 External Clock (SCK) External clocking is used in the synchronous or SPI slave mode of operation. External clock input from the SCK pin is sampled by a synchronization logic to remove meta-stability. The output from the synchronization logic must be passed through an edge detector before it is used by the transmitter and receiver.
MC96F8204 ABOV Semiconductor Co., Ltd. 11.8.6 UART Data format A serial frame is defined to be one character of data bits with synchronization bits (start and stop bits), and optionally a parity bit for error detection. The USART supports all 30 combinations of the following as valid frame formats.
MC96F8204 ABOV Semiconductor Co., Ltd. 11.8.7 UART Parity bit The parity bit is calculated by doing an exclusive-OR of all the data bits. If odd parity is used, the result of the exclusive-OR is inverted. The parity bit is located between the MSB and first stop bit of a serial frame.
MC96F8204 ABOV Semiconductor Co., Ltd. UART Parity Generator 11.8.8.3 The parity generator calculates the parity bit for the serial frame data to be sent. When parity bit is enabled (USTP1=1), the transmitter control logic inserts the parity bit between the MSB and the first stop bit of the frame to be sent.
MC96F8204 ABOV Semiconductor Co., Ltd. UART Receiver Flag and Interrupt 11.8.9.2 The UART receiver has one flag that indicates the receiver state. The receive complete (RXC) flag indicates whether there are unread data in the receive buffer. This flag is set when there is unread data in the receive buffer and cleared when the receive buffer is empty.
MC96F8204 ABOV Semiconductor Co., Ltd. Asynchronous Data Reception 11.8.9.5 To receive asynchronous data frame, the USART includes a clock and data recovery unit. Theclock recovery logic is used for synchronizing the internally generated baud-rate clock to the incoming asynchronous serial frame on the RXD pin.
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MC96F8204 ABOV Semiconductor Co., Ltd. When the receiver is enabled (RXE=1), the clock recovery logic tries to find a high-to-low transition on the RXD line, the start bit condition. After detecting high to low transition on RXD line, the clock recovery logic uses samples 8, 9 and 10 for normal mode to decide if a valid start bit is received.
MC96F8204 ABOV Semiconductor Co., Ltd. 11.8.10 SPI Mode The USART can be set to operate in industrial standard SPI compliant mode. The SPI mode has the following features. − Full Duplex, Three-wire synchronous data transfer − Mater and Slave Operation −...
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MC96F8204 ABOV Semiconductor Co., Ltd. (CPOL=0) (CPOL=1) SAMPLE MOSI MSB First … BIT7 BIT6 BIT2 BIT1 BIT0 LSB First … BIT0 BIT1 BIT5 BIT6 BIT7 MISO /SS OUT (MASTER) /SS IN (SLAVE) Figure 11.32 USART SPI Clock Formats when CPHA=0 When CPHA=0, the slave begins to drive its MISO output with the first data bit value when SS goes to active low.
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MC96F8204 ABOV Semiconductor Co., Ltd. (CPOL=0) (CPOL=1) SAMPLE MOSI … MSB First BIT7 BIT6 BIT2 BIT1 BIT0 … LSB First BIT0 BIT1 BIT5 BIT6 BIT7 MISO /SS OUT (MASTER) /SS IN (SLAVE) Figure 11.33 USART SPI Clock Formats when CPHA=1 When CPHA=1, the slave begins to drive its MISO output when SS goes active low, but the data is not defined until the first SCK edge.
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MC96F8204 ABOV Semiconductor Co., Ltd. USTCR2 (USART Control Register 2) : DAH DRIE TXCIE RXCIE WAKEIE USTEN DBLS Initial value : 00H URIE Interrupt enable bit for Data Register Interrupt from DRE is inhibited (use polling) When DRE is set, request an interrupt...
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MC96F8204 ABOV Semiconductor Co., Ltd. USTCR3 (USART Control Register 3) : DBH MASTER LOOPS DISSCK USTSSEN FXCH USTSB USTTX8 USTRX8 Initial value : 00H MASTER Selects master or slave in SPI or Synchronous mode operation and controls the direction of SCK pin.
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MC96F8204 ABOV Semiconductor Co., Ltd. USTST (USART Status Register) : DCH WAKE USTRST Initial value : 80H The DRE flag indicates if the transmit buffer (USTDR) is ready to receive new data. If DRE is ‘1’, the buffer is empty and ready to be written. The flag can generate a DRE interrupt.
MC96F8204 ABOV Semiconductor Co., Ltd. 11.9 11.9.1 Overview The I2C is one of industrial standard serial communication protocols, and which uses 2 bus lines Serial Data Line (SDA) and Serial Clock Line (SCL) to exchange data. Because both SDA and SCL lines are open-drain output, each line needs pull-up resistor.
MC96F8204 ABOV Semiconductor Co., Ltd. 11.9.3 I2C Bit Transfer The data on the SDA line must be stable during HIGH period of the clock, SCL. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW. The exceptions are START(S), repeated START(Sr) and STOP(P) condition where data line changes when clock line is high.
MC96F8204 ABOV Semiconductor Co., Ltd. 11.9.5 Data Transfer Every byte put on the SDA line must be 8-bits long. The number of bytes that can be transmitted per transfer is unlimited. Each byte has to be followed by an acknowledge bit. Data is transferred with the most significant bit (MSB) first.
MC96F8204 ABOV Semiconductor Co., Ltd. 11.9.6 I2C Acknowledge The acknowledge related clock pulse is generated by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDA line during the acknowledge clock pulse so that it remains stable LOW during the HIGH period of this clock pulse.
MC96F8204 ABOV Semiconductor Co., Ltd. 11.9.7 Synchronization / Arbitration Clock synchronization is performed using the wired-AND connection of I2C interfaces to the SCL line. This means that a HIGH to LOW transition on the SCL line will cause the devices concerned to start counting off their LOW period and it will hold the SCL line in that state until the clock HIGH state is reached.
MC96F8204 ABOV Semiconductor Co., Ltd. 11.9.8 Operation The I2C is byte-oriented and interrupt based. Interrupts are issued after all bus events except for a transmission of a START condition. Because the I2C is interrupt based, the application software is free to carry on other operations during a I2C byte transfer.
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MC96F8204 ABOV Semiconductor Co., Ltd. 3) Master transmits repeated START condition with not checking ACK signal. In this case, load SLA+R/W into the I2CDR and set STARTC bit in I2CCR. After doing one of the actions above, clear to “0b” all interrupt source bits in I2CSR to release SCL line. In case of 1), move to step 7.
MC96F8204 ABOV Semiconductor Co., Ltd. Master Receiver 11.9.8.2 To operate I2C in master receiver, follow the recommended steps below. Enable I2C by setting IICEN bit in I2CCR. This provides main clock to the peripheral. Load SLA+R into the I2CDR where SLA is address of slave device and R is transfer direction from the viewpoint of the master.
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MC96F8204 ABOV Semiconductor Co., Ltd. I2C can choose one of the following cases according to the RXACK flag in I2CSR. 1) Master continues receiving data from slave. To do this, set ACKEN bit in I2CCR to Acknowledge the next data to be received.
MC96F8204 ABOV Semiconductor Co., Ltd. I2C Slave Transmitter 11.9.8.3 To operate I2C in slave transmitter, follow the recommended steps below. If the main operating clock (SCLK) of the system is slower than that of SCL, load value 0x00 into I2CSDHR to make SDA change within one system clock period from the falling edge of SCL.
MC96F8204 ABOV Semiconductor Co., Ltd. Slave Receiver 11.9.8.4 To operate I2C in slave receiver, follow the recommended steps below. If the main operating clock (SCLK) of the system is slower than that of SCL, load value 0x00 into I2CSDHR to make SDA change within one system clock period from the falling edge of SCL. Note that the hold time of SDA is calculated by SDAH x period of SCLK where SDAH is multiple of number of SCLK coming from I2CSDHR.
MC96F8204 ABOV Semiconductor Co., Ltd. 11.9.11 Register Description for I2C I2CDR (I2C Data Register) : ECH I2CDR7 I2CDR6 I2CDR5 I2CDR4 I2CDR3 I2CDR2 I2CDR1 I2CDR0 Initial value : 00H I2CDR[7:0] The I2CDR transmit buffer and receive buffer share the same I/O address with this DATA register.
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MC96F8204 ABOV Semiconductor Co., Ltd. I2CSAR0 (I2C Slave Address 0 Register) : EBH I2CSLA06 I2CSLA05 I2CSLA04 I2CSLA03 I2CSLA02 I2CSLA01 I2CSLA00 GCALL0EN Initial value : 00H I2CSLA0[6:0] These bits configure the slave address 0 in slave mode. GCALL0EN This bit decides whether I2C allows general call address or not in I2C slave mode.
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MC96F8204 ABOV Semiconductor Co., Ltd. I2CCR (I2C Control Register) : E9H IICRST IICEN TXDLYENB IICIE ACKEN IMASTER STOPC STARTC Initial value : 00H IICRST Initialize Internal Registers of I2C. No effect Initialize I2C, auto cleared IICEN Activate I2C Function Block by Supplying.
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MC96F8204 ABOV Semiconductor Co., Ltd. I2CSR (I2C Status Register) : EAH GCALL TEND STOPD SSEL MLOST BUSY TMODE RXACK Initial value : 00H (NOTE) GCALL This bit has different meaning depending on whether I2C is master or slave. When I2C is a master, this bit represents whether it received ACK (address ACK) from slave.
MC96F8204 ABOV Semiconductor Co., Ltd. 11.10 FLASH CRC/Checksum Generator 11.10.1 Overview The Flash CRC(cyclic redundancy check) generator is used to get a 16-bit CRC code from Flash ROM and a generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the functional safety standards, they offer a means of verifying the Flash memory integrity.
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MC96F8204 ABOV Semiconductor Co., Ltd. The CRC operation procedure in Auto CRC/Checksum mode Global interrupt Disable (EA = 0) Select Auto CRC/Checksum Mode and CRC Select CRC Clock Set CRC start address register (FCSARH/FCSARM/FCSARL) Set CRC end address register (FCEARH/FCEARM/FCEARL)
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MC96F8204 ABOV Semiconductor Co., Ltd. The CRC operation procedure in User CRC/Checksum mode Select User CRC/Checksum Mode and CRC Clear Flash CRC data register(FCDRH/FCDRL) Read data from the Flash ROM Write the data to FCDIN Register Read the CRC result Program Tip –...
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MC96F8204 ABOV Semiconductor Co., Ltd. The Checksum operation procedure in Auto CRC/Checksum mode Global interrupt Disable (EA = 0) Select Auto CRC/Checksum Mode and Checksum Select CRC Clock Set CRC start address register (FCSARH/FCSARM/FCSARL) Set CRC end address register (FCEARH/FCEARM/FCEARL)
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MC96F8204 ABOV Semiconductor Co., Ltd. The Checksum operation procedure in User CRC/Checksum mode Select User CRC/Checksum Mode and Checksum Clear Flash CRC data register(FCDRH/FCDRL) Read data from the Flash ROM Write the data to FCDIN Register Read the Checksum result Program Tip –...
MC96F8204 ABOV Semiconductor Co., Ltd. 11.10.3 Flash CRC Generator Register Description The flash CRC generator register consists of flash CRC start address high/middle/low register (FCSARH/ FCSARM/FCSARL), flash CRC end address high/middle/low register (FCEARH/FCEARM/FCEARL), flash CRC control register (FCCR), flash CRC data high/low register (FCDRH/FCDRL) and flash CRC data In register (FCDIN).
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MC96F8204 ABOV Semiconductor Co., Ltd. FCEARH (Flash CRC End Address High Register): 5051H – – – – – – – FCEARH0 – – – – – – – Initial value: 00H FCEARH0 Flash CRC End Address High NOTE) Used only to Auto CRC Mode.
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MC96F8204 ABOV Semiconductor Co., Ltd. FCDIN (Flash CRC Data IN Register): D7H FCDIN7 FCDIN6 FCDIN5 FCDIN4 FCDIN3 FCDIN2 FCDIN1 FCDIN0 Initial value: 00H FCDIN[7:0] Flash CRC Data In NOTE) Used only to Auto CRC Mode. FCCR (Flash CRC Control Register): 5056H –...
MC96F8204 ABOV Semiconductor Co., Ltd. Power Down Operation 12.1 Overview The MC96F8204 has two power-down modes to minimize the power consumption of the device. In power down mode, power consumption is reduced considerably. The device provides three kinds of power saving functions, Main-IDLE, Sub-IDLE and STOP mode.
MC96F8204 ABOV Semiconductor Co., Ltd. 12.3 IDLE Mode The power control register is set to ‘01h’ to enter the IDLE Mode. In this mode, the internal oscillation circuits remain active. Oscillation continues and peripherals are operated normally but CPU stops. It is released by reset or interrupt.
MC96F8204 ABOV Semiconductor Co., Ltd. 12.4 STOP Mode The power control register is set to ‘03H’ to enter the STOP Mode. In the stop mode, the selected oscillator, system clock and peripheral clock is stopped, but watch timer can be continued to operate with sub clock. With the clock frozen, all functions are stopped, but the on-chip RAM and control registers are held.
MC96F8204 ABOV Semiconductor Co., Ltd. 12.5 Release Operation of STOP Mode After STOP mode is released, the operation begins according to content of related interrupt register just before STOP mode start (Figure 12.3). If the global interrupt Enable Flag (IE.EA) is set to `1`, the STOP mode is released by the interrupt which each interrupt enable flag = `1` and the CPU jumps to the relevant interrupt service routine.
MC96F8204 ABOV Semiconductor Co., Ltd. 12.6 Register Map Name Address Direction Default Description PCON Power Control Register Power Down Operation Register Map Table 12.2 12.7 Power Down Operation Register Description The power down operation register consists of the power control register (PCON).
MC96F8204 ABOV Semiconductor Co., Ltd. RESET 13.1 Overview The following is the hardware setting value. On Chip Hardware Initial Value Program Counter (PC) 0000h Accumulator Stack Pointer (SP) Peripheral Clock Control Register Refer to the Peripheral Registers Reset State Table 13.1 13.2...
MC96F8204 ABOV Semiconductor Co., Ltd. 13.4 RESET Noise Canceller The Figure 13.2 is the noise canceller diagram for noise cancellation of RESET. It has the noise cancellation value of about 2us(@V =5V) to the low input of system reset. t < T t <...
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MC96F8204 ABOV Semiconductor Co., Ltd. Counting for config read start after POR is released Internal nPOR PAD RESETB “H” LVR_RESETB .. 27 28 BIT (for Config) 00 01 02 03 BIT (for Reset) 1us X 256 X 28h = about 10ms...
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MC96F8204 ABOV Semiconductor Co., Ltd. Process Description Remarks ① - No Operation ② - 1st POR level Detection - about 1.4V - (INT-OSC 8MHz/8)x256x28h Delay section (=10ms) - Slew Rate >= 0.05V/ms ③ - VDD input voltage must rise over than flash operating voltage for Config read - about 1.5V ~ 1.6V...
MC96F8204 ABOV Semiconductor Co., Ltd. 13.6 External RESETB Input The External RESETB is the input to a Schmitt trigger. If RESETB pin is held with low for at least 10us over within the operating voltage range and stable oscillation, it is applied and the internal state is initialized. After reset state becomes ‘1’, it needs the stabilization time with 16ms and after the stable state, the internal RESET becomes ‘1’.
MC96F8204 ABOV Semiconductor Co., Ltd. 13.7 Brown Out Detector Processor The MC96F8204 has an On-chip brown-out detection circuit (BOD) for monitoring the VDD level during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be selected by LVRVS[3:0] bit to be 1.60V, 2.05V, 2.15V, 2.25V,2.37V, 2.50V, 2.65V, 2.82V, 3.01V, 3.22V, 3.47V, 3.76V, 4.10V, 4.51V.
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MC96F8204 ABOV Semiconductor Co., Ltd. “H” “H” Internal nPOR “H” PAD RESETB LVR_RESETB BIT (for Config) ..27 28 00 01 02 BIT (for Reset) 1us X 256 X 28h = about 10ms Config Read 1us X 4096 X 4h = about 16ms...
MC96F8204 ABOV Semiconductor Co., Ltd. 13.11 Register Description for Reset Operation RSTFR (Reset Flag Register) : E8H – – – PORF EXTRF WDTRF OCDRF LVRF – – – Initial value : 80H Power-On Reset flag bit. The bit is reset by writing ‘0’ to this bit.
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MC96F8204 ABOV Semiconductor Co., Ltd. LVRCR (Low Voltage Reset Control Register) : D8H – – LVRST LVRVS3 LVRVS2 LVRVS1 LVRVS0 LVREN – – Initial value : 00H LVRST LVR Enable when Stop Release Not effect at stop release LVR enable at stop release NOTE) When this bit is ‘1’, the LVREN bit is cleared to ‘0’...
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MC96F8204 ABOV Semiconductor Co., Ltd. LVICR (Low Voltage Indicator Control Register) : 86H – – LVIF LVIEN LVILS3 LVILS2 LVILS1 LVILS0 – – Initial value : 00H LVIF Low Voltage Indicator Flag Bit No detection Detection LVIEN LVI Enable/Disable Disable...
MC96F8204 ABOV Semiconductor Co., Ltd. On-chip Debug System 14.1 Overview 14.1.1 Description On-chip debug system (OCD) of MC96F8204 can be used for programming the non-volatile memories and on-chip debugging. Detail descriptions for programming via the OCD interface can be found in the following chapter.
MC96F8204 ABOV Semiconductor Co., Ltd. 14.1.2 Feature − Two-wire external interface: 1-wire serial clock input, 1-wire bi-directional serial data bus − Debugger Access to: • All Internal Peripheral Units • Internal data RAM • Program Counter • Flash and Data EEPROM Memories −...
MC96F8204 ABOV Semiconductor Co., Ltd. 14.2 Two-Pin External Interface 14.2.1 Basic Transmission Packet • 10-bit packet transmission using two-pin interface. • 1-packet consists of 8-bit data, 1-bit parity and 1-bit acknowledge. • Parity is even of ‘1’ for 8-bit data in transmitter.
MC96F8204 ABOV Semiconductor Co., Ltd. 14.2.2 Packet Transmission Timing Data Transfer 14.2.2.1 DSDA acknowledgement acknowledgement signal from receiver signal from receiver DSCL START STOP Figure 14.3 Data Transfer on the Twin Bus Bit Transfer 14.2.2.2 DSDA DSCL data line change...
MC96F8204 ABOV Semiconductor Co., Ltd. Start and Stop Condition 14.2.2.3 DSDA DSDA DSCL DSCL START condition STOP condition Figure 14.5 Start and Stop Condition Acknowledge Bit 14.2.2.4 Data output By transmitter no acknowledge Data output By receiver acknowledge DSCL from...
MC96F8204 ABOV Semiconductor Co., Ltd. 14.2.3 Connection of Transmission Two-pin interface connection uses open-drain(wire-AND bidirectional I/O). pull - up resistors DSDA(Debugger Serial Data Line) DSCL(Debugger Serial Clock Line) DSCL DSDA DSCL DSDA DSDA DSDA DSCL DSCL Target Device(Slave) Host Machine(Master) Current source for DSCL to fast 0 to 1 transition in high speed mode Figure 14.8...
MC96F8204 ABOV Semiconductor Co., Ltd. Flash Memory 15.1 Overview 15.1.1 Description MC96F8204 incorporates flash memory to which a program can be written, erased, and overwritten while mounted on the board. The flash memory can be read by ‘MOVC’ instruction and it can be programmed in OCD, serial ISP mode or user program mode.
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MC96F8204 ABOV Semiconductor Co., Ltd. FMCR (Flash Mode Control Register) : FEH – – – – FMBUSY FMCR2 FMCR1 FMCR0 – – – – Initial value : 00H FMBUSY Flash Mode Busy Bit. This bit will be used for only debugger.
MC96F8204 ABOV Semiconductor Co., Ltd. 15.1.6 Serial In-System Program (ISP) Mode Serial in-system program uses the interface of debugger which uses two wires. Refer to chapter 14 in details about debugger 15.1.7 Protection Area (User program mode) MC96F8204 can program its own flash memory (protection area). The protection area can not be erased or programmed.
MC96F8204 ABOV Semiconductor Co., Ltd. 15.1.8 Erase Mode The sector erase program procedure in user program mode Page buffer clear (FMCR=0x01) Write ‘0’ to page buffer Set flash sector address register (FSADRH/FSADRM/FSADRL). Set flash identification register (FIDR). (Note) Check the UserID for to prevent the invalid work Set flash mode control register (FMCR).
MC96F8204 ABOV Semiconductor Co., Ltd. 15.1.9 Write Mode The sector Write program procedure in user program mode Page buffer clear (FMCR=0x01) Write data to page buffer Set flash sector address register (FSADRH/FSADRM/FSADRL). Set flash identification register (FIDR). (Note1) Check the UserID for to prevent the invalid work Set flash mode control register (FMCR).
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MC96F8204 ABOV Semiconductor Co., Ltd. The Byte Write program procedure in user program mode Page buffer clear (FMCR=0x01) Write data to page buffer Set flash sector address register (FSADRH/FSADRM/FSADRL). Set flash identification register (FIDR). (Note1) Check the UserID for to prevent the invalid work Set flash mode control register (FMCR).
MC96F8204 ABOV Semiconductor Co., Ltd. 15.1.10 Protection for Invalid Erase/Write It should be taken care to the flash erase/write programming in code. You must make preparations for invalid jump to the flash erase/write code by malfunction, noise, and power off.
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MC96F8204 ABOV Semiconductor Co., Ltd. The flash sector address (FSADRH/FSADRM/FSADRL) should always keep the address of the flash which is used for data area. For example, The FSADRH/FSADRM is always 0x00/0x0f” if 0x0f00 to 0x0fff is used for data. Overview of main...
MC96F8204 ABOV Semiconductor Co., Ltd. Flow of Protection for Invalid Erase/Write 15.1.10.1 Start Work1 Decide to write/erase Set Flags on flash Work2 Check the flag for Match Write UserID1/2/3 UserID Work3 Check the UserID for Match Write/Erase Flash write/erase flash...
MC96F8204 ABOV Semiconductor Co., Ltd. 15.1.11 Read Mode The Reading program procedure in user program mode Load receive data from flash memory on MOVC instruction by indirectly addressing mode. Program Tip – reading A,#0 DPH,#0x0F DPL,#0xA0 ;flash memory address MOVC A,@A+DPTR ;read data from flash memory...
MC96F8204 ABOV Semiconductor Co., Ltd. Configure Option 16.1 Configure Option Control The data for configure option should be written in the configure option area (001EH – 001FH) by programmer (Writer tools). CONFIGURE OPTION 1 : ROM Address 001FH – –...
MC96F8204 ABOV Semiconductor Co., Ltd. APPENDIX 17.1 Instruction Table Instructions are either 1, 2 or 3bytes long as listed in the ‘Bytes’ column below. Each instruction takes either 1, 2 or 4 machine cycles to execute as listed in the following table. 1 machine cycle comprises 2 system clock cycles.
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MC96F8204 ABOV Semiconductor Co., Ltd. LOGICAL Mnemonic Description Bytes Cycles Hex code ANL A,Rn AND register to A 58-5F ANL A,dir AND direct byte to A ANL A,@Ri AND indirect memory to A 56-57 ANL A,#data AND immediate to A...
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MC96F8204 ABOV Semiconductor Co., Ltd. DATA TRANSFER Mnemonic Description Bytes Cycles Hex code MOV A,Rn Move register to A E8-EF MOV A,dir Move direct byte to A MOV A,@Ri Move indirect memory to A E6-E7 MOV A,#data Move immediate to A...
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MC96F8204 ABOV Semiconductor Co., Ltd. BRANCHING Mnemonic Description Bytes Cycles Hex code ACALL addr 11 Absolute jump to subroutine 11→F1 LCALL addr 16 Long jump to subroutine Return from subroutine RETI Return from interrupt AJMP addr 11 Absolute jump unconditional 01→E1...
MC96F8204 ABOV Semiconductor Co., Ltd. 17.2 Flash Protection for Invalid Erase/Write Overview This is example to prevent changing code or data in flash by abnormal operation(noise, unstable power, malfunction, etc…). How to protect the flash • Divide into decision and execution to Erase/Write in flash.
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MC96F8204 ABOV Semiconductor Co., Ltd. Flowchart Start Initial ① Set LVR/LVI more than 2.0V Start Main Loop Working ③ Write Flash? Set User_ID1 ② Working ③ Check User_ID1? Set User_ID2 Working Check User_ID2? Set User_ID3 ③ Working Write Flash Set FSADDRH/M/L ④...
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Initialize User_ID1/2/3 Set Flash Sector Address to Dummy Address • Sample Source Refer to the ABOV homepage. It is created based on the MC97F2664. Each product should be modified according to the Page Buffer Size and Flash Size Etc •...
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