Interrupt Sequence - Abov MC80F0304 User Manual

MC80F0304/08/16
IRQH
INT0IF
MSB
IRQL
MSB

18.1 Interrupt Sequence

An interrupt request is held until the interrupt is accepted or the
interrupt latch is cleared to "0" by a reset or an instruction. Inter-
rupt acceptance sequence requires 8 cycles of f
Interrupt acceptance
1. The interrupt master enable flag (I-flag) is cleared to
"0" to temporarily disable the acceptance of any follow-
ing maskable interrupts. When a non-maskable inter-
rupt is accepted, the acceptance of any following
interrupts is temporarily disabled.
2. The contents of the program counter (return address)
and the program status word are saved (pushed) onto the
96
R/W R/W R/W R/W R/W
INT1IF INT2IF INT3IF
UARTRIF UARTTIF
R/W R/W R/W - R/W
T1IF T2IF T3IF - ADCIF WDTIF
Figure 18-3 Interrupt Request Flag Register
(2μs at f
XIN
R/W R/W R/W
ADDRESS: 0EC
T0IF
SIOIF
INITIAL VALUE: 0000 0000
LSB
Timer/Counter 0 interrupt request flag
Serial Communication interrupt request flag
UART Tx interrupt request flag
UART Rx interrupt request flag
External interrupt 3 request flag
External interrupt 2 request flag
External interrupt 1 request flag
External interrupt 0 request flag
R/W - R/W
ADDRESS: 0ED
- BITIF
INITIAL VALUE: 000- 00-0
LSB
Basic Interval Timer interrupt request flag
Watchdog timer interrupt request flag
A/D Converter interrupt request flag
Timer/Counter 3 interrupt request flag
Timer/Counter 2 interrupt request flag
Timer/Counter 1 interrupt request flag
=4MHz) after the completion of the current instruction
IN
execution. The interrupt service task is terminated upon execu-
tion of an interrupt return instruction [RETI].
X-
stack area. The stack pointer decreases 3 times.
3. The entry address of the interrupt service program is
read from the vector table address and the entry address
is loaded to the program counter.
4. The instruction stored at the entry address of the inter-
H
B
H
B
November 4, 2011 Ver 2.12