Stop Mode At Internal Rc-Oscillated Watchdog Timer Mode - Abov MC80F0304 User Manual

MC80F0304/08/16
STOP Mode
Oscillator (XI pin)
Internal Clock
RESET
Internal RESET
STOP Instruction Execution Stabilization Time
Time can not be control by software t ST = 65.5mS @4MHz
Figure 19-6 Timing of STOP Mode Release by Reset

19.3 Stop Mode at Internal RC-Oscillated Watchdog Timer Mode

In the Internal RC-Oscillated Watchdog Timer mode, the on-chip (at RC-watchdog timer mode). Reset re-defines all the Control
lated in this mode. The on-chip RAM and Control registers are oscillator is stopped. But internal RC oscillation circuit is oscil- registers but does not change the on-chip RAM. External inter- rupts allow both on-chip RAM and Control registers to retain
held. The port pins out the values held by their respective port their values.
data register, port direction registers. If I-flag = 1, the normal interrupt response takes place. In this
The Internal RC-Oscillated Watchdog Timer mode is activated case, if the bit WDTON of CKCTLR is set to "0" and the bit
by execution of STOP instruction after setting the bit RCWDT of CKCTLR to "1". (This register should be written by byte opera- dog timer interrupt service routine(Figure 8-6 ). However, if the WDTE of IENH is set to "1", the device will execute the watch-
tion. If this register is set by bit manipulation instruction, for ex- bit WDTON of CKCTLR is set to "1", the device will generate
ample "set1" or "clr1" instruction, it may be undesired operation) 19-8 ). If I-flag = 0, the chip will resume execution starting with the internal Reset signal and execute the reset processing(Figure
the instruction following the STOP instruction. It will not vector
Note: Caution: After STOP instruction, at least two or more NOP to interrupt service routine.(refer to Figure 19-4 )
instruction should be written When exit from Stop mode at Internal RC-Oscillated Watchdog
Ex) LDM WDTR,#1111_1111B LDM CKCTLR,#0010_1110B Timer mode by external interrupt, the oscillation stabilization time is required to normal operation. Figure 19-7 shows the tim-
LDM SSCR,#0101_1010B ing diagram. When release the Internal RC-Oscillated Watchdog
NOP STOP ;for stabilization time Timer mode, the basic interval timer is activated on wake-up. It
NOP ;for stabilization time normal operation. Therefore, before STOP instruction, user must is increased from 00 until FF H . The count overflow is set to start H
be set its relevant prescaler divide ratio to have long enough time
The exit from Internal RC-Oscillated Watchdog Timer mode is (more than 20msec). This guarantees that oscillator has started
hardware reset or external interrupt or watchdog timer interrupt dog Timer mode is shown in Figure 19-8 . and stabilized. By reset, exit from internal RC-Oscillated Watch-
106 November 4, 2011 Ver 2.12