Abov MC95FG0128A Manuals

Manuals and User Guides for Abov MC95FG0128A. We have 1 Abov MC95FG0128A manual available for free PDF download: User Manual

Abov MC95FG0128A User Manual

Abov MC95FG0128A User Manual (201 pages)

8-BIT

Brand: Abov | Category: Microcontrollers | Size: 3 MB

Table of Contents

Revision History
2
Table of Contents
4
List of Figures
7
1 Overview

10
- Description
  10
- Features
  10
- Ordering Information
  12
- Figure 1.1 Device Nomenclature
  12
- Development Tools
  13
- Figure 1.2 Debugger and Pin Description
  13
- Figure 1.3 OCD Interface Circuit
  14
- Figure 1.4 E-PGM+ Component and Connector
  15
- Figure 1.5 Pgmpluslc Writer
  16
- Figure 1.6 E-PGM+ Gang4/6 Programmer
  17
2 Block Diagram

18
3 Pin Assignmnet

21
- Figure 3.1 MC95FG0128A 100 Pin LQFP Assignment
  21
- Figure 3.2 MC95FG0128A 80 Pin LQFP Assignment
  22
4 Package Diagram

26
5 Pin Description

31
6 Port Structures

35
7 Electrical Characteristics

37
- Absolute Maximum Ratings
  37
- Recommended Operating Conditions
  37
- A/D Converter Characteristics
  38
- Voltage Dropout Converter Characteristics
  38
- Power-On Reset Characteristics
  39
- Brown out Detector Characteristics
  39
- Internal RC Oscillator Characteristics
  39
- Ring-Oscillator Characteristics
  40
- PLL Characteristics
  40
- DC Characteristics
  41
- AC Characteristics
  42
- Figure 7.1 AC Timing
  42
- SPI Characteristics
  43
- Figure 7.2 SPI Timing
  43
- Typical Characteristics
  44
8 Memory

45
- Program Memory
  45
- Figure 8.1 Program Memory
  46
- Data Memory
  47
- Figure 8.2 Data Memory Map
  47
- Figure 8.3 Lower 128 Bytes RAM
  48
- EEPROM Data Memory and XSRAM
  49
- Figure 8.4 XDATA Memory Area
  49
- SFR Map
  50
9 I/O Ports

54
- Port Register
  54
- Px Port
  57
10 Interrupt Controller

59
11 Peripheral Hardware

74
12 Power down Operation

159
13 Reset

164
- Overview
  164
- Reset Source
  164
- Block Diagram
  164
- Figure 13.1 RESET Block Diagram
  164
- RESET Noise Canceller
  165
- Power on RESET
  165
- Figure 13.2 Reset Noise Canceller Time Diagram
  165
- Figure 13.3 Fast VDD Rising Time
  165
- Figure 13.4 Internal RESET Release Timing on Power-Up
  166
- Figure 13.5 Configuration Timing When Power-On
  166
- Figure 13.6 Boot Process Wave Form
  167
- External RESETB Input
  168
- Figure 13.7 Timing Diagram after RESET
  168
- Figure 13.8 Oscillator Generating Waveform Example
  168
- Brown out Detector Processor
  169
- Figure 13.9 Block Diagram of BOD
  169
- Figure 13.10 Internal Reset at the Power Fail Situation
  169
- Figure 13.11 Configuration Timing When BOD RESET
  170
14 On-Chip Debug System

172
15 Memory Programming

177

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